View MB91F278SPMC_4253601.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16801-2E
32-bit Microcontroller
CMOS
FR60Lite MB91270 Series
MB91F273(S)/MB91F278(S)/MB91V280
DESCRIPTION
The MB91270 series is single chip microcontroller that builds various I/O resources and the bus control mechanisms into by using 32-bit efficient RISC CPU for the built-in control being demanded for CPU processing high performance/high-speed. RAM (for reading data) is included in order to support CPU to access to the vast address space and to speed up the execution of CPU instructions. This series is optimized to the embedded applications; automotive applications such as car audio or car air-conditioning equipment that require high-performance CPU processing power. It is designed based on the FR-family* CPU. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
FEATURES
* FR CPU characteristics * 32-bit RISC, load/store architecture with a five-stage pipeline * Maximum operating frequency: 32 MHz (using the PLL at an oscillation frequency of 4 MHz) * 16-bit fixed length instructions (basic instructions), 1 instruction per cycle * Function entry/exit instructions, multiple - register load/store instructions : Instructions adapted for high - level languages * Memory-to-memory transfer, bit manipulation, barrel shift instruction etc.: Instruction optimized for embedded applications (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2005-2007 FUJITSU LIMITED All rights reserved
MB91270 Series
* Register interlock functions: Easier assembler coding enabled * Built-in multiplier supported at the instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles * Interrupt (PC, PS save): 6 cycles, 16 priority levels * Harvard architecture allowing program access and data access to be executed simultaneously * Instruction compatible with FR family * External bus interface * Maximum operating frequency: 16 MHz * Can output full 24-bit address range (16 Mbyte space) * 8,16-bit data output * Unused data/address pin can be used as general-purpose I/O ports. * Capable of chip select output for completely independent four areas settable in 64 Kbytes minimum. * Supports the following memory interfaces SRAM, ROM/Flash * Basic bus cycle: 2 cycles * Programmable automatic wait cycle generation function capable of inserting wait cycles for each area * RDY input for external wait cycles * Built-in memory MB91V280 ROM/Flash F-bus RAM External SRAM 48 Kbytes MB91F273 (S) Flash 512 Kbytes 24 Kbytes MB91F278 (S) Flash 512 Kbytes 24 Kbytes
The peripheral circuits are described below. Refer to "PRODUCT LINEUP" for the number of available channels on each model. * DMAC (DMA Controller) * Capable of simultaneous operation of up to five channels * Two forwarding factors (internal peripheral/software) * Bit search module (for REALOS) Search for the first position of the bit "1"/ "0" changed in one word from the MSB * LIN UARTs (LIN-UART) : Up to 7 channels * Asynchronous (start-stop synchronous) communications, clock synchronous communications * Synch-Break detection * Built-in baud rate generator on each channel * Supports SPI (mode 2: Clock synchronous communication mode) * CAN CONTROLLERS : 3 channels (Max) * High-speed transfer : 1 Mbps * 32 message buffer (128 message buffer on the MB91V280) (Continued)
2
MB91270 Series
* Various timers * 16-bit reload timer : 3 channels (including one channel for REALOS) The internal clock can be divided by 2, 8, or 32 * 16-bit free-running timer: 4 channels Output compare module: 8 channels Input capture module: 8 channels * 8/16-bit PPG timer: 8-bit x 16 channels or 16-bit x 8 channels * Interrupt controller * Interrupt from internal peripheral * Software-selectable priority level (16 levels) * D/A converter : 2 channels 8-bit or 10-bit resolution, R-2R type * A/D converter: 24 channels (MB91V280 has an additional module with eight more channels) * 10-bit resolution * Successive approximation conversion type Conversion time : 3 s * Conversion mode (single conversion mode, continuous conversion mode) * Activation source (software, external trigger, peripheral interrupt) * Other interval timer/counter * 8/16-bit up down counter : 8 bits x 4 channels or 16 bits x 2 channels * 16-bit timebase timer / watchdog timer * I2C bus interface* (400 kbps): 3 channels * Master/slave sending and receiving * Arbitration and clock synchronization * Hardware watchdog Interval time: 569 ms (Min), 771 ms (Max) (Use of self-oscillation circuit with timing (100 kHz) ) * I/O port * Pull-up/pull-down can be controlled independently for each pin. * The input level for each pin can be set to either CMOS Schmitt trigger levels or CMOS automotive Schmitt trigger levels. * The pin level can be read directly. * Max 82 ports * Other features * Internal oscillator circuit as clock source, allowing PLL multiplication to be selected * INIT is prepared as a reset pin. * Watchdog timer reset, software reset * Available low-power consumption modes are stop mode, sleep mode, and real time clock mode. Supports low-power consumption operation with CPU operating at 32 kHz ("s" without only product). * Gear function * Built-in timebase timer * Wild register (Continued) 3
MB91270 Series
(Continued) * Output clock (clock monitor) * Clock Modulator * Clock supervisor Uses an internal self-oscillation circuit to monitor whether the main clock halts (MB91F278 (S) only) . * Package PGA-401, LQFP-100 * CMOS technology (0.35 m) * Power supply voltage: 3.5 V to 5.5 V The 3.3 V supply to internal circuits is generated by an internal step-down circuit. * : I2C license Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
4
MB91270 Series
PRODUCT LINEUP
Kind Parameter Package Built-in ROM/ Flash RAM External bus External interrupt DMAC (DMA Controller) Clock modulator Clock supervisor Clock monitor 32 kHz sub-clock Real time clock CAN controllers LIN UARTs (LIN-UART) I2C interface 16-bit reload timer 8/16-bit up down counter 16-bit free-run timer Input capture Output compare 8/16-bit PPG 10-bit A/D converter 8/10-bit D/A converter Pin pull-up/down Input level selector Debugging support 1 channel (32 message buffer) 7 channels 3 channels 3 channels 2 channels 4 channels 8 channels 8 channels 16-bit x 8 channels 8-bit x 16 channels 24 channels No Refer to "PIN FUNCTION" Refer to "PIN FUNCTION" Wild register 24 channels + 8 channels 2 channels All pins All pins DSU4 No Yes Option (Models without S-suffix part number only) Yes 3 channels (128 message buffer) Yes MB91F273 (S) LQFP-100 Flash 512 Kbytes 24 Kbytes Address : 24 bits Data : 16 bits (Multiplex only) 16 channels 5 channels Yes Yes MB91F278 (S) LQFP-100 Flash 512 Kbytes 24 Kbytes MB91V280 PGA-401 External SRAM 48 Kbytes Address : 24 bits Data : 16 bits 40 channels
5
MB91270 Series
PIN ASSIGNMENT
(TOP VIEW)
P26/A22/IN2 P27/A23/IN3 P30/AS/IN4 P31/RD/IN5 P32/WR0/RX2/INT10R P33/WR1/TX2 P34/BRQ/OUT4 P35/BGRNT/OUT5 P36/RDY/OUT6 P37/SYSCLK/OUT7 P40/(X0A) P41/(X1A) VCC VSS C P42/IN6/RX1/INT9R P43/IN7/TX1 P44/SDA0/FRCK0 P45/AIN2/SCL0/FRCK1 P46/BIN2/SDA1 P47/ZIN2/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/BIN1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P25/A21/IN1 P24/A20/IN0 P23/A19/PPGF P22/A18/PPGD P21/A17/PPGB P20/A16/PPG9 P17/AD15/SCK4 P16/AD14/SOT4 P15/AD13/SIN4 X0 X1 VSS VCC P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/INT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/SCK6/INT13 P04/AD04/SOT6/INT12 P03/AD03/SIN6/INT11 P02/AD02/SCK5/INT10 P01/AD01/SOT5/INT9
LQFP-100
P00/AD00/SIN5/INT8 PA1/TX0 PA0/RX0/INT8R P97/OUT3 P96/OUT2/ZIN0 P95/OUT1/BIN0 P94/OUT0/AIN0 P93/PPG7/ZIN3/CS3 P92/PPG5/BIN3/CS2 P91/PPG3/AIN3/CS1 P90/PPG1/CS0 VSS VCC P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/TOT2/SOT0 P82/TIN2/SIN0/INT14R P81/TOT0/INT13R/CKOT P80/TIN0/INT12R/ADTG P77/AN23/INT7/SCL2 P76/AN22/INT6/SDA2 INIT MD0
6
P54/AN12/AIN1 P55/AN13/ZIN1 P56/AN14/DAO0 P57/AN15/DAO1 AVCC AVRH AVRL AVSS P60/AN0/PPG0 P61/AN1/PPG2 P62/AN2/PPG4 P63/AN3/PPG6 P64/AN4/PPG8 P65/AN5/PPGA P66/AN6/PPGC P67/AN7/PPGE VSS P70/AN16/INT0 P71/AN17/INT1 P72/AN18/INT2 P73/AN19/INT3 P74/AN20/INT4 P75/AN21/INT5 MD2 MD1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(FPT-100P-M05)
MB91270 Series
PIN FUNCTION
Pin No. 90 91 52 Pin name X1 X0 INIT Function name X1 X0 INIT I/O circuit type* OB OA N J Oscillator output pin Oscillator input pin Reset input pin ("L" active) Operation mode select input pins. Connect to VCC or VSS directly. Port 0 P00 75 P00/AD00/ SIN5/INT8 AD00 INT8 SIN5 P01 76 P01/AD01/ SOT5/INT9 AD01 INT9 SOT5 P02 77 P02/AD02/ SCK5/INT10 AD02 INT10 SCK5 P03 78 P03/AD03/ SIN6/INT11 AD03 INT11 SIN6 P04 79 P04/AD04/ SOT6/INT12 AD04 INT12 SOT6 T T T T T General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 0 This function is enabled when the external bus is enabled. External interrupt request 8 input pin Serial data input pin for LIN-UART5 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 1 This function is enabled when the external bus is enabled. External interrupt request 9 input pin Serial data output pin for LIN-UART5 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 2 This function is enabled when the external bus is enabled. External interrupt request 10 input pin Clock I/O pin for LIN-UART5 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 3 This function is enabled when the external bus is enabled. External interrupt request 11 input pin Serial data input pin for LIN-UART6 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 4 This function is enabled when the external bus is enabled. External interrupt request 12 input pin Serial data output pin for LIN-UART6 (Continued) Function
49 to 51 MD2 to MD0 MD2 to MD0
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
7
MB91270 Series
Pin No. Pin name Function name P05 80 P05/AD05/ SCK6/INT13 AD05 INT13 SCK6 P06 81 P06/AD06/ INT14 AD06 INT14 P07 82 P07/AD07/ INT15 AD07 INT15 T T T I/O circuit type* Function General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 5 This function is enabled when the external bus is enabled. External interrupt request 13 input pin Clock I/O pin for LIN-UART6 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 6 This function is enabled when the external bus is enabled. External interrupt request 14 input pin General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 7 This function is enabled when the external bus is enabled. External interrupt request 15 input pin Port 1 P10 83 P10/AD08/ TIN1 AD08 TIN1 P11 84 P11/AD09/ TOT1 AD09 TOT1 P12 85 P12/AD10/ SIN3/ INT11R AD10 SIN3 INT11R P13 86 P13/AD11/ SOT3 AD11 SOT3 T T T T General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 8 This function is enabled when the external bus is enabled. Event input pin for reload timer 1 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 9 This function is enabled when the external bus is enabled. Output pin for reload timer 1 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 10 This function is enabled when the external bus is enabled. Serial data input pin for LIN-UART3 External interrupt request 11 input pin (Set by EISSR) General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 11 This function is enabled when the external bus is enabled. Serial data output pin for LIN-UART3 (Continued)
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
8
MB91270 Series
Pin No. Pin name Function name P14 87 P14/AD12/ SCK3 AD12 SCK3 P15 92 P15/AD13/ SIN4 AD13 SIN4 P16 93 P16/AD14/ SOT4 AD14 SOT4 P17 94 P17/AD15/ SCK4 AD15 SCK4 T T T T I/O circuit type* Function General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 12 This function is enabled when the external bus is enabled. Clock I/O pin for LIN-UART3 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 13 This function is enabled when the external bus is enabled. Serial data input pin for LIN-UART4 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 14 This function is enabled when the external bus is enabled. Serial data output pin for LIN-UART4 General-purpose I/O port. This function is enabled in single-chip mode. External address/data bus I/O pin bit 15 This function is enabled when the external bus is enabled. Clock I/O pin for LIN-UART4 Port 2 P20 95 P20/A16/ PPG9 A16 PPG9 P21 96 P21/A17/ PPGB A17 PPGB P22 97 P22/A18/ PPGD A18 PPGD A A A General-purpose I/O port. This function is enabled in single-chip mode. External address bus output pin bit 16 This function is enabled when the external bus is enabled. Output pin for PPG9 General-purpose I/O port. This function is enabled in single-chip mode. External address bus output pin bit 17 This function is enabled when the external bus is enabled. Output pin for PPGB General-purpose I/O port. This function is enabled in single-chip mode. External address bus output pin bit 18 This function is enabled when the external bus is enabled. Output pin for PPGD (Continued)
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
9
MB91270 Series
Pin No. Pin name Function name P23 98 P23/A19/ PPGF A19 PPGF P24 to P27 99, 100, 1, 2 P24/A20/IN0 to A20 to A23 P27/A23/IN3 IN0 to IN3 A A I/O circuit type* Function General-purpose I/O port. This function is enabled in single-chip mode. External address bus output pin bit 19 This function is enabled when the external bus is enabled. Output pin for PPGF General-purpose I/O port. This function is enabled in single-chip mode. External address bus output pins bits 20 to 23 This function is enabled when the external bus is enabled. Data sample input pins for input capture ICU0 to ICU3 Port 3 P30 3 P30/AS/IN4 AS IN4 P31 4 P31/RD/IN5 RD IN5 P32 P32/WR0/ RX2/ INT10R A A General-purpose I/O port. This function is enabled in single-chip mode. External address strobe output pin This function is enabled when the external bus is enabled. Data sample input pin for input capture ICU4 General-purpose I/O port. This function is enabled in single-chip mode. External read strobe output pin This function is enabled when the external bus is enabled. Data sample input pin for input capture ICU5 General-purpose I/O port. This function is enabled in single-chip mode. External data bus write strobe output pin. Enabled when the external bus is enabled. WR0 is used as the data write strobe for 8-bit access and as the upper 8 bits of the data in 16-bit access. CAN2 RX input pin (MB91V280 only) External interrupt request 10 input pin (Set by EISSR) General-purpose I/O port. This function is enabled in single-chip mode. A Write strobe output pin for lower 8 bits in external data bus Enabled when the external bus is enabled and external bus 16-bit mode is selected. CAN2 TX output pin (MB91V280 only) (Continued)
5
WR0
A
RX2 INT10R P33 6 P33/WR1/ TX2
WR1 TX2
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
10
MB91270 Series
Pin No. Pin name Function name P34 P34/BRQ/ OUT4 I/O circuit type* Function General-purpose I/O port. This function is enabled in single-chip mode. T (A) External bus request input pin Enabled when the external bus and the bus request functions are enabled. (MB91V280 only) Waveform output pin for output compare OCU4. General-purpose I/O port. This function is enabled in single-chip mode. A External bus acknowledge output pin Enabled when the external bus and the bus request functions are enabled. (MB91V280 only) Waveform output pin for output compare OCU5. General-purpose I/O port. This function is enabled in single-chip mode. T External ready input pin Enabled when the external bus and the bus request functions are enabled. Waveform output pin for output compare OCU6. General-purpose I/O port. This function is enabled in single-chip mode. A External clock output pin This function is enabled when the external bus is enabled. Waveform output pin for output compare OCU7. Port 4 P40/ (X0A) , P41/ (X1A) P40, P41 X0A, X1A P42 16 P42/IN6/ RX1/INT9R IN6 RX1 INT9R P43 17 P43/IN7/ TX1 IN7 TX1 P44 18 P44/SDA0/ FRCK0 SDA0 FRCK0 C A A A WA WB General-purpose I/O port (S-suffix models) sub-clock oscillator input pin (without S-suffix models) General-purpose I/O port Data sample input pin for input capture ICU6 CAN1 RX input pin (MB91V280 only) External interrupt request 9 input pin (Set by EISSR) General-purpose I/O port Data sample input pin for input capture ICU7 CAN1 TX output pin (MB91V280 only) General-purpose I/O port Serial data I/O pin for I2C0 16-bit input/output timer 0 input pin (Continued) 11
7
BRQ
OUT4 P35 P35/ BGRNT/ OUT5
8
BGRNT
OUT5 P36 9 P36/RDY/ OUT6
RDY OUT6 P37
10
P37/ SYSCLK/ OUT7
SYSCLK OUT7
11, 12
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
MB91270 Series
Pin No. Pin name Function name P45 19 P45/AIN2/ SCL0/ FRCK1 SCL0 FRCK1 AIN2 P46 20 P46/BIN2/ SDA1 SDA1 BIN2 P47 21 P47/ZIN2/ SCL1 SCL1 ZIN2 P50 22 P50/AN8/ SIN2 AN8 SIN2 P51 23 P51/AN9/ SOT2 AN9 SOT2 P52 24 P52/AN10/ SCK2 AN10 SCK2 P53 25 P53/AN11/ BIN1 AN11 BIN1 P54 26 P54/AN12/ AIN1 AN12 AIN1 P55 27 P55/AN13/ ZIN1 AN13 ZIN1 P56 28 P56/AN14/ DAO0 AN14 DAO0 P57 29 P57/AN15/ DAO1 AN15 DAO1 E E D D D D D D C C C I/O circuit type* Function General-purpose I/O port Serial clock I/O pin for I2C0 16-bit input/output timer 1 input pin 8/16-bit up-count input pin for up down counter 2/3 General-purpose I/O port Serial clock I/O pin for I2C1 8/16-bit down-count input pin for up down counter 2/3 General-purpose I/O port Serial clock I/O pin for I2C1 8/16-bit reset input pin for up down counter 2/3 Port 5 General-purpose I/O port Analog input pin of A/D converter Serial data input pin for LIN-UART2 General-purpose I/O port Analog input pin of A/D converter Serial data output pin for LIN-UART2 General-purpose I/O port Analog input pin of A/D converter Clock I/O pin for LIN-UART2 General-purpose I/O port Analog input pin of A/D converter 8-bit down-count input pin for 16-bit up down counter 1 General-purpose I/O port Analog input pin of A/D converter 8-bit up-count input pin for 16-bit up down counter 1 General-purpose I/O port Analog input pin of A/D converter 8-bit reset input pin for 16-bit up down counter 1 General-purpose I/O port Analog input pin of A/D converter Analog output pin 0 for D/A converter (MB91V280 only) General-purpose I/O port Analog input pin of A/D converter Analog output pin 1 for D/A converter (MB91V280 only) (Continued) 12
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
MB91270 Series
Pin No. Pin name Function name P60 to P67 AN0 to AN7 P60/AN0/ PPG0 to P67/AN7/ PPGE PPG0 PPG2 PPG4 PPG6 PPG8 PPGA PPGC PPGE P70 to P75 AN16 to AN21 INT0 to INT5 P76 53 P76/AN22/ INT6/SDA2 AN22 INT6 SDA2 P77 54 P77/AN23/ INT7/SCL2 AN23 INT7 SCL2 P80 55 P80/TIN0/ INT12R/ ADTG TIN0 ADTG INT12R P81 56 P81/TOT0/ INT13R/ CKOT TOT0 CKOT INT13R P82 57 P82/TIN2/ SIN0/INT14R SIN0 TIN2 INT14R A A A CA CA D I/O circuit type* Port 6 General-purpose I/O port Analog input pins of A/D converter Function
34 to 41
D Output pins for PPG
Port 7 P70/AN16/ INT0 to P75/AN21/ INT5 General-purpose I/O port Analog input pins of A/D converter External interrupt request 0 to 5 input pin General-purpose I/O port Analog input pin of A/D converter External interrupt request 6 input pin Serial clock I/O pin for I2C2 General-purpose I/O port Analog input pin of A/D converter External interrupt request 7 input pin Serial clock I/O pin for I2C2 Port 8 General-purpose I/O port Event input pin for reload timer 0 Trigger input pin for A/D converter External interrupt request 12 input pin (Set by EISSR) General-purpose I/O port Output pin for reload timer 0 Output pin for clock monitor External interrupt request 13 input pin (Set by EISSR) General-purpose I/O port Serial data input pin for LIN-UART0 Event input pin for reload timer 2 External interrupt request 14 input pin (Set by EISSR) (Continued) 13
43 to 48
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
MB91270 Series
Pin No. Pin name P83/TOT2/ SOT0 Function name P83 58 SOT0 TOT2 P84 59 P84/SCK0/ INT15R SCK0 INT15R 60 61 62 P85/SIN1 P86/SOT1 P87/SCK1 P85 SIN1 P86 SOT1 P87 SCK1 P90 65 P90/PPG1/ CS0 CS0 PPG1 P91 66 P91/PPG3/ AIN3/CS1 CS1 PPG3 AIN3 P92 67 P92/PPG5/ BIN3/CS2 CS2 PPG5 BIN3 P93 68 P93/PPG7/ ZIN3/CS3 CS3 PPG7 ZIN3 P94 69 P94/OUT0/ AIN0 OUT0 AIN0 A A A A A A A A A A I/O circuit type* Function General-purpose I/O port Serial data output pin for LIN-UART0 Output pin for reload timer 2 General-purpose I/O port Clock I/O pin for LIN-UART0 External interrupt request 15 input pin (Set by EISSR) General-purpose I/O port Serial data input pin for LIN-UART1 General-purpose I/O port Serial data output pin for LIN-UART1 General-purpose I/O port Clock I/O pin for LIN-UART1 Port 9 General-purpose I/O port External chip select 0 This function is enabled when the external bus is enabled. Output pin for PPG1 General-purpose I/O port External chip select 1 This function is enabled when the external bus is enabled. Output pin for PPG3 8-bit up-count input pin for up down counter 3 General-purpose I/O port External chip select 2 This function is enabled when the external bus is enabled. Output pin for PPG5 8-bit down-count input pin for up down counter 3 General-purpose I/O port External chip select 3 This function is enabled when the external bus is enabled. Output pin for PPG7 8-bit reset input pin for up down counter 3 General-purpose I/O port Waveform output pin for output compare OCU0 16/8-bit up-count input pin for up down counter 0/1 (Continued)
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
14
MB91270 Series
Pin No. Pin name P95/OUT1/ BIN0 Function name P95 70 OUT1 BIN0 P96 71 P96/OUT2/ ZIN0 OUT2 ZIN0 72 P97/OUT3 P97 OUT3 PA0 73 PA0/RX0/ INT8R RX0 INT8R 74 PA1/TX0 PA1 TX0 PB0 PB0 INT8-2 SIN5-2 PB1 PB1 INT9-2 SOT5-2 PB2 PB2 INT10-2 SCK5-2 PB3 PB3 INT11-2 SIN6-2 PB4 PB4 INT12-2 SOT6-2 PB5 PB5 INT13-2 SCK6-2 A A A A A A A A A A A I/O circuit type* Function General-purpose I/O port Waveform output pin for output compare OCU1 8/16-bit down-count input pin for up down counter 0/1 General-purpose I/O port Waveform output pin for output compare OCU2 8/16-bit reset input pin for up down counter 0/1 General-purpose I/O port Waveform output pin for output compare OCU3 Port A General-purpose I/O port RX input pin for CAN0 External interrupt request 8 input pin (Set by EISSR) General-purpose I/O port TX output pin for CAN0 General-purpose I/O port External interrupt request 8 input pin (Set by EPFRB) Serial data input pin for LIN-UART5 (Set by PFRB) General-purpose I/O port External interrupt request 9 input pin (Set by EPFRB) Serial data output pin for LIN-UART5 General-purpose I/O port External interrupt request 10 input pin (Set by EPFRB) Clock I/O pin for LIN-UART5 (set by PFRB) General-purpose I/O port External interrupt request 11 input pin (Set by EPFEB) Serial data input pin for LIN-UART6 (Set by PFRB) General-purpose I/O port External interrupt request 12 input pin (Set by EPFRB) Serial data output pin for LIN-UART6 General-purpose I/O port External interrupt request 13 input pin (Set by EPFRB) Clock I/O pin for LIN-UART6 (set by PFRB) Port C (MB91V280 only) * : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type. (Continued)
Port B (MB91V280 only)
15
MB91270 Series
Pin No. Pin name Function name PC0 PC0 OUT4-2 INT0R PC1 PC1 OUT5-2 INT1R PC2 PC2 SIN3-2 INT2R PC3 PC3 SOT3-2 INT3R PC4 PC4 SCK3-2 INT4R PC5 PC5 SIN4-2 INT5R PC6 PC6 SOT4-2 INT6R PC7 PC7 SCK4-2 INT7R PD0 PD0 INT16 PPG9-2 PD1 PD1 INT17 PPGB-2 PD2 PD2 INT18 PPGD-2 A A A A A A A A A A A I/O circuit type* Function General-purpose I/O port Output pin for output compare 4 External interrupt request 0 input pin (Set by EISSR) General-purpose I/O port Output pin for output compare 5 External interrupt request 1 input pin (Set by EISSR) General-purpose I/O port Serial data input pin for LIN-UART3 (Set by PFRC) External interrupt request 2 input pin (Set by EISSR) General-purpose I/O port Serial data output pin for LIN-UART3 External interrupt request 3 input pin (Set by EISSR) General-purpose I/O port Clock I/O pin for LIN-UART3 (set by PFRC) External interrupt request 4 input pin (Set by EISSR) General-purpose I/O port Serial data input pin for LIN-UART4 (Set by PFRC) External interrupt request 5 input pin (Set by EISSR) General-purpose I/O port Serial data output pin for LIN-UART4 External interrupt request 6 input pin (Set by EISSR) General-purpose I/O port Clock I/O pin for LIN-UART4 (set by PFRC) External interrupt request 7 input pin (Set by EISSR) Port D (MB91V280 only) General-purpose I/O port External interrupt request 16 input pin Output pin for PPG9 (8) General-purpose I/O port External interrupt request 17 input pin Output pin for PPGB (A) General-purpose I/O port External interrupt request 18 input pin Output pin for PPGD (C) (Continued)
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
16
MB91270 Series
Pin No. Pin name Function name PD3 PD3 INT19 PPGF-2 PD4 PD4 INT20 IN0-2 PD5 PD5 INT21 IN1-2 PD6 PD6 INT22 IN2-2 PD7 PD7 INT23 IN3-2 PE0 PE0 A00 INT24 PE1 PE1 A01 INT25 PE2 PE2 A02 INT26 PE3 PE3 A03 INT27 PE4 PE4 A04 INT28 A A A A A A A A A A I/O circuit type* Function General-purpose I/O port External interrupt request 19 input pin Output pin for PPGF (E) General-purpose I/O port External interrupt request 20 input pin Input pin for input capture ICU0 (set by PFRD) General-purpose I/O port External interrupt request 21 input pin Input pin for input capture ICU1 (set by PFRD) General-purpose I/O port External interrupt request 22 input pin Input pin for input capture ICU2 (set by PFRD) General-purpose I/O port External interrupt request 23 input pin Input pin for input capture ICU3 (set by PFRD) Port E (MB91V280 only) General-purpose I/O port External address bus output pin bit 0 This function is enabled when the external bus is enabled. External interrupt request 24 input pin General-purpose I/O port External address bus output pin bit 1 This function is enabled when the external bus is enabled. External interrupt request 25 input pin General-purpose I/O port External address bus output pin bit 2 This function is enabled when the external bus is enabled. External interrupt request 26 input pin General-purpose I/O port External address bus output pin bit 3 This function is enabled when the external bus is enabled. External interrupt request 27 input pin General-purpose I/O port External address bus output pin bit 4 This function is enabled when the external bus is enabled. External interrupt request 28 input pin (Continued)
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
17
MB91270 Series
Pin No. Pin name Function name PE5 PE5 A05 INT29 PE6 PE6 A06 INT30 PE7 PE7 A07 INT31 PF0 PF0 A08 INT32 PF1 PF1 A09 INT33 PF2 PF2 A10 INT34 PF3 PF3 A11 INT35 PF4 PF4 A12 INT36 PF5 PF5 A13 INT37 A A A A A A A A A I/O circuit type* Function General-purpose I/O port External address bus output pin bit 5 This function is enabled when the external bus is enabled. External interrupt request 29 input pin General-purpose I/O port External address bus output pin bit 6 This function is enabled when the external bus is enabled. External interrupt request 30 input pin General-purpose I/O port External address bus output pin bit 7 This function is enabled when the external bus is enabled. External interrupt request 31 input pin Port F (MB91V280 only) General-purpose I/O port External address bus output pin bit 8 This function is enabled when the external bus is enabled. External interrupt request 32 input pin General-purpose I/O port External address bus output pin bit 9 This function is enabled when the external bus is enabled. External interrupt request 33 input pin General-purpose I/O port External address bus output pin bit 10 This function is enabled when the external bus is enabled. External interrupt request 34 input pin General-purpose I/O port External address bus output pin bit 11 This function is enabled when the external bus is enabled. External interrupt request 35 input pin General-purpose I/O port External address bus output pin bit 12 This function is enabled when the external bus is enabled. External interrupt request 36 input pin General-purpose I/O port External address bus output pin bit 13 This function is enabled when the external bus is enabled. External interrupt request 37 input pin (Continued)
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
18
MB91270 Series
(Continued) Pin No. Pin name Function name PF6 PF6 A14 INT38 PF7 PF7 A15 INT39 PG0 AN24 PG1 AN25 PG2 AN26 PG3 AN27 PG4 AN28 PG5 AN29 PG6 AN30 PG7 AN31 A A I/O circuit type* Function General-purpose I/O port External address bus output pin bit 14 This function is enabled when the external bus is enabled. External interrupt request 38 input pin General-purpose I/O port External address bus output pin bit 15 This function is enabled when the external bus is enabled. External interrupt request 39 input pin Port G (MB91V280 only) PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 D D D D D D D D General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter Power supply pin 13, 63, 88 14, 42, 64, 89 15 30 31 32 33 VCC VSS C AVCC AVRH AVRL AVSS Power supply (5 V) input pin Power supply (0 V) input pin Power stabilization capacitance pin Analog power supply input pin Reference voltage input pin for the A/D converter Ensure that a voltage greater than AVRH is applied to AVCC when turning this power supply on or off. Low reference voltage input pin for the A/D converter Analog VSS input pin
* : Refer to " I/O CIRCUIT TYPE" for the I/O circuit type.
19
MB91270 Series
I/O CIRCUIT TYPE
Type Circuit Pull-up control Remarks * CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS hysteresis input (With function to disconnect input during standby mode. ) * Automotive input (With function to disconnect input during standby mode. ) * Resistor that can be set pull-up resistor : Approx. 50
P-ch N-ch
P-ch N-ch
Pout Nout
A Pull-down control CMOS hysteresis input Automotive input Standby control for disconnect input
P-ch N-ch
Pout Nout
B CMOS hysteresis input Automotive input Standby control for disconnect input
* CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS hysteresis input (With function to disconnect input during standby mode. ) * Automotive input (With function to disconnect input during standby mode. )
P-ch N-ch
Pout Nout
C CMOS hysteresis input Automotive input Standby control for disconnect input
* CMOS level output (IOL = 3 mA, IOH = -3 mA) * CMOS hysteresis input (With function to disconnect input during standby mode. ) * Automotive input (With function to disconnect input during standby mode. )
(Continued)
20
MB91270 Series
Type
Circuit
Remarks * CMOS level output (IOL = 3 mA, IOH = -3 mA) * CMOS hysteresis input (With function to disconnect input during standby mode. ) * Automotive input (With function to disconnect input during standby mode. ) * A/D analog input
P-ch N-ch
Pout Nout
CA
CMOS hysteresis input Automotive input Standby control for disconnect input Analog input Pull-up control
P-ch N-ch
P-ch N-ch
Pout Nout
D
Pull-down control CMOS hysteresis input Automotive input Standby control for disconnect input Analog input
* CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS hysteresis input (With function to disconnect input during standby mode. ) * Automotive input (With function to disconnect input during standby mode. ) * Resistor that can be set pull-up resistor : Approx. 50 * A/D analog input
(Continued)
21
MB91270 Series
Type Circuit Remarks * CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS hysteresis input (With function to disconnect input during standby mode. ) * Automotive input (With function to disconnect input during standby mode. ) * A/D analog input * D/A analog output
P-ch N-ch
Pout Nout
CMOS hysteresis input E Automotive input Standby control for disconnect input Analog input
Analog output CMOS hysteresis input J CMOS hysteresis input * CMOS hysteresis input * Pull-up resistor value : Approx. 50 k CMOS hysteresis input * CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS hysteresis input (With function to disconnect input during standby mode. ) * Automotive input (With function to disconnect input during standby mode. ) * TTL (With function to disconnect input during standby mode. ) * Resistor that can be set pull-up resistor : Approx. 50 k
N
Pull-up resistor
Pull-up control
P-ch N-ch
P-ch N-ch
Pout Nout
T
Pull-down control CMOS hysteresis input Automotive input TTL input Standby control for disconnect input
(Continued) 22
MB91270 Series
(Continued) Type
X1
Circuit
Xout
Remarks Oscillation circuit High speed oscillation feedback resistance = Approx. 1 M
OA OB
X0
Standby control signal Oscillation circuit Low speed oscillation feedback resistance = Approx. 10 M
X1A
Xout
WA WB
X0A
Standby control signal
23
MB91270 Series
I/O CELL LIST
Input Type Pull Up/Down (50 k) Up/Down switch Up/Down switch Up Up/Down switch CMOS (C) CMOS Schmitt (CS) Automotive (A) CS/A switch CS/A switch CS/A switch CS/A switch CS/A switch CS/A switch C CS (initx) CS/A/TTL switch Input Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Analog Line Output Driver Input Input I/O Remarks
A B C* CA* D E J N T OA OB WA WB
4 mA 4 mA 3 mA 3 mA 4 mA 4 mA 4 mA I2C I2C + A/DC A/DC A/DC + D/AC MD[2 : 0] INIT Has TTL input 4 MHz Oscillator 32 kHz Oscillator
* : When the C and CA ports are set for the use of an I2C interface, the outputs are Nch open drain outputs. Otherwise, functions as a CMOS output.
PIN INPUT VOLTAGE
Form C CS (initx) CS A T CMOS input CMOS Schmitt trigger input (for INIT pin) CMOS Schmitt trigger input CMOS automotive Schmitt trigger input TTL input Type VIL VSS + 0.3 V 0.2 x VCC 0.3 x VCC 0.5 x VCC 0.8 V VIH VCC - 0.3 V 0.8 x VCC 0.7 x VCC 0.8 x VCC 2.1 V
24
MB91270 Series
HANDLING DEVICES
* Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC pin and VSS pin. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, do not exceed the maximum rating. * Treatment of Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. * Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations such as latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device. * Crystal Oscillator Circuit Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, X0A and X1A pins the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. * Notes on Using External Clock When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode (oscillation stop mode) must not be used. (This is because the X1 pin stops at High level output in STOP mode.)
Using an external clock (normal)
X0 X1
Note : The STOP mode (oscillation stop mode) cannot be used.
25
MB91270 Series
* Notes when using no sub-clock Use a single-clock model if not using the sub-clock. Always connect a resonator of 100 kHz or less on dual clock models. * Treatment of NC or OPEN pins Pins marked as NC and OPEN must be left open - circuit. * Mode pins (MD0 to MD2) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. * Operation at start-up The INIT pin must be held at the "L"level when turning on the power. * Source oscillation input at power on When turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state. * Caution on operations during PLL Clock Mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. * External bus setting This device is guaranteed for use with a 16 MHz external bus. If the base clock is set to 32 MHz with DIVR1 (external bus base clock division setting register) set to its initial value, the external bus also operates at 32 MHz. When changing the base clock, set the external bus so that it will not exceed 16 MHz. * Pull-up control The AC characteristics cannot be guaranteed if pull-up resistors are used for the pins used as external bus pins.
26
MB91270 Series
BLOCK DIAGRAM
Clock generator
FR 60 Lite CPU CORE
Watchdog timer Voltage regulator
32
Bit search module Debug support DMA controller
32
I-bus
D-bus
Flash/ MASK ROM
Harvard bus converter
32
32
F-bus
F-busRAM
32
External bus 24-bit address 16-bit data
CAN controller
External bus I/F
R-bus adapter 16 8/10-bit D/AC
Clock supervisor
Hardware watchdog
10-bit A/DC
LINUART0
R-bus sub-clock
LINUART
16-bit reload timer
Clock monitor
Real time clock
ICU 16 bits
16-bit free-run timer
Output Compare 16 bits
I2C 400 kHz
External interrupt
Up down counter 8/16 bits
PPG 8/16 bits
27
MB91270 Series
MEMORY MAP
MB91V280 0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 0000H 0002 0500H 0003 4000H
Built-in RAM 48 Kbytes
Access prohibited
MB91F273 (S)/ MB91F278 (S) I/O I/O
Access prohibited
Direct addressing area Refer to "I/O MAP"
CAN
Access prohibited
CAN
Access prohibited
0003 A000H 0003 D800H 0004 0000H
Built-in RAM 24 Kbytes
Access prohibited
Access prohibited
0008 0000H
Emulation SRAM area Flash 512 Kbytes
0010 0000H External area FFFF FFFFH External area
Note : The initial value for the emulation SRAM area on the MB91V280 is 512 Kbytes (0000080000H to 0000100000H) . An SRAM area is supported up to 1024 Kbytes (0000050000H to 0000150000H)
28
MB91270 Series
I/O MAP
How to read I/O map Address
000000H
Register +0
PDR0 [R/W] B XXXXXXXX
+1
PDR1 [R/W] B XXXXXXXX
+2
PDR2 [R/W] B XXXXXXXX
+3
PDR3 [R/W] B XXXXXXXX
Block
T-unit Port data register
Read/Write attribute, Access unit (B : byte, H : halfword, W : word) Initial value after reset Register name (First-column register at address 4n; second-column register at 4n + 1, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : " 1 " : Initial value "1" " 0 " : Initial value "0" " X " : Initial value "undefined" "-" : No physical register present at this location Access by any undescribed data access attribute is prohibited.
29
MB91270 Series
Address 000000H 000004H 000008H 00000CH 000010H 000014H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH
Register +0 PDR0 [R/W] B, H XXXXXXXX PDR4 [R/W] B, H XXXXXXXX PDR8 [R/W] B, H XXXXXXXX +1 PDR1 [R/W] B, H XXXXXXXX PDR5 [R/W] B, H XXXXXXXX PDR9 [R/W] B, H XXXXXXXX +2 PDR2 [R/W] B, H XXXXXXXX PDR6 [R/W] B, H XXXXXXXX PDRA [R/W] B, H ------XX +3 PDR3 [R/W] B, H XXXXXXXX PDR7 [R/W] B, H XXXXXXXX PDRB [R/W] B, H --XXXXXX
Block
Port Data Registers
PDRC [R/W] B, H PDRD [R/W] B, H PDRE [R/W] B, H XXXXXXXX XXXXXXXX XXXXXXXX PDRG [R/W] B, H XXXXXXXX EIRR0 [R/W] 00000000 DICR [R/W] -------0 ENIR [R/W] 00000000 HRCL [R, R/W] 0--11111
(PDRB to PDRG are only available PDRF [R/W] B, H on the MB91V280.) XXXXXXXX
System Reserved ELVR0 [R/W] 00000000 00000000 TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R, RW] 00000000 00000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R, RW] 00000000 00000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R, RW] 00000000 00000000 SSR0 [R, R/W] 00001000 BGR10 [R/W] 00000000 SSR5 [R, R/W] 00001000 BGR15 [R/W] 00000000 RDR0/TRD0 [R/W] 00000000 BGR00 [R/W] 00000000 RDR5/TRD5 [R/W] 00000000 BGR05 [R/W] 00000000 (Continued)
Ext. INT 0-7 DLY / I-Unit
TMRLR0 [W] XXXXXXXX XXXXXXXX TMRLR1 [W] XXXXXXXX XXXXXXXX TMRLR2 [W] XXXXXXXX XXXXXXXX SCR0 [R, R/W] 00000000 ESCR0 [R/W] 00000100 SCR5 [R, R/W] 00000000 ESCR5 [R/W] 00000100 SMR0 [W, R/W] 00000000 ECCR0 [R, W, R/W] 000000XX SMR5 [W, R/W] 00000000 ECCR5 [R, W, R/W] 000000XX
Reload Timer 0
Reload Timer 1
Reload Timer 2
000060H
LIN-UART 0
000064H
000068H
LIN-UART 5
00006CH
30
MB91270 Series
Register +0 SCR6 [R, R/W] 00000000 ESCR6 [R/W] 00000100 +1 SMR6 [W, R/W] 00000000 ECCR6 [R, W, R/W] 000000XX SCR1 [R, R/W] 00000000 ESCR1 [R/W] 00000100 SCR2 [R, R/W] 00000000 ESCR2 [R/W] 00000100 SCR3 [R, R/W] 00000000 ESCR3 [R/W] 00000100 SCR4 [R, R/W] 00000000 ESCR4 [R/W] 00000100 EIRR1 [R/W] 00000000 SMR1 [W, R/W] 00000000 ECCR1 [R, W, R/W] 000000XX SMR2 [W, R/W] 00000000 ECCR2 [R, W, R/W] 000000XX SMR3 [W, R/W] 00000000 ECCR3 [R, W, R/W] 000000XX SMR4 [W, R/W] 00000000 ECCR4 [R, W, R/W] 000000XX ENIR1 [R/W] 00000000 SSR1 [R, R/W] 00001000 BGR11 [R/W] 00000000 SSR2 [R, R/W] 00001000 BGR12 [R/W] 00000000 SSR3 [R, R/W] 00001000 BGR13 [R/W] 00000000 SSR4 [R, R/W] 00001000 BGR14 [R/W] 00000000 RDR1/TRD1 [R/W] 00000000 BGR01 [R/W] 00000000 RDR2/TRD2 [R/W] 00000000 BGR02 [R/W] 00000000 RDR3/TRD3 [R/W] 00000000 BGR03 [R/W] 00000000 RDR4/TRD4 [R/W] 00000000 BGR04 [R/W] 00000000 Ext. INT 8 to 15 Free-run Timer 0 Free-run Timer 1 Free-run Timer 2 Free Run Timer 3 (Continued) 31 +2 SSR6 [R, R/W] 00001000 BGR16 [R/W] 00000000 +3 RDR6/TRD6 [R/W] 00000000 BGR06 [R/W] 00000000
Address
Block
000070H
LIN-UART 6
000074H 000078H to 0000ACH 0000B0H
System Reserved
LIN-UART 1
0000B4H
0000B8H
LIN-UART 2
0000BCH
0000C0H
LIN-UART 3
0000C4H
0000C8H
LIN-UART 4
0000CCH
0000D0H 0000D4H 0000D8H 0000DCH 0000E0H
ELVR1 [R/W] 00000000 00000000 TCCS0 [R/W] B 00000000 TCCS1 [R/W] B 00000000 TCCS2 [R/W] B 00000000 TCCS3 [R/W] B 00000000
TCTDT0 [R/W] H 00000000 00000000 TCTDT1 [R/W] H 00000000 00000000 TCTDT2 [R/W] H 00000000 00000000 TCTDT3 [R/W] H 00000000 00000000
MB91270 Series
Register +0 +1 +2 +3 IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX IPCP5 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX OCS23 [R/W] 11101100 00001100 OCCP5 [R/W] XXXXXXXX XXXXXXXX OCCP7 [R/W] XXXXXXXX XXXXXXXX OCS67 [R/W] 11101100 00001100 EIRR2 [R/W] 00000000 EIRR3 [R/W] 00000000 EIRR4 [R/W] 00000000 ENIR2 [R/W] 00000000 ENIR3 [R/W] 00000000 ENIR4 [R/W] 00000000 DACR [R/W] -----000 ELVR2 [R/W] 00000000 00000000 ELVR3 [R/W] 00000000 00000000 ELVR4 [R/W] 00000000 00000000 DADR0 [R/W] ------00 00000000 DADBL [R/W] -------0 OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX OCS01 [R/W] 11101100 00001100 OCCP4 [R/W] XXXXXXXX XXXXXXXX OCCP6 [R/W] XXXXXXXX XXXXXXXX OCS45 [R/W] 11101100 00001100 IPCP0 [R] XXXXXXXX XXXXXXXX ICS01 [R/W] 00000000 IPCP2 [R] XXXXXXXX XXXXXXXX ICS23 [R/W] 00000000 IPCP4 [R] XXXXXXXX XXXXXXXX ICS45 [R/W] 00000000 IPCP6 [R] XXXXXXXX XXXXXXXX ICS67 [R/W] 00000000
Address 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH 000110H 000114H 000118H 00011CH 000120H to 00012CH 000130H 000134H 000138H 00013CH 000140H
Block
Input Capture Unit 0, 1
Input Capture Unit 2, 3
Input Capture Unit 4, 5
Input Capture Unit 6, 7 System Reserved Output Compare 1/0 Output Compare 3/2 Output Compare 3 to 0 Ctrl. Output Compare 5/4 Output Compare 7/6 Output Compare 7 to 4 Ctrl. System Reserved
Ext. INT 16 to 23 Ext. INT 24 to 31 (MB91V280 only) Ext. INT 32 to 39 (MB91V280 only) D/A Converter (MB91V280 only) (Continued)
DADR1 [R/W] ------00 00000000
32
MB91270 Series
Register +0 +1 WTDBL [R/W] B ------00 +2 +3 WTCR [R/W] B, H 00000000 000-00-X Real Time Clock
Address 000144H 000148H 00014CH 000150H 000154H 000158H 00015CH 000160H 000164H to 00016CH 000170H
Block
WTBR [R/W] B ---XXXXX XXXXXXXX XXXXXXXX WTSR [R/W] B --XXXXXX
WTHR [R/W] B, H WTMR [R/W] B, H XXXXXXXX XXXXXXXX ADERH [R/W] 00000000 00000000 ADCS1 [R/W] 00000000 ADCT1 [R/W] 00010000 ADCS0 [R, R/W] 00000000 ADCT0 [R/W] 00101100
ADERL [R/W] 00000000 00000000 ADCR1 [R] ------XX ADSCH [R/W] ---00000 ADCR0 [R] XXXXXXXX ADECH [R/W] ---00000 Clock Calibration (MB91V280 and without S-suffix models only) System Reserved UDCR1 [R] B, H 00000000 UDCR0 [R] B, H 00000000 UDCS0 [R/W] B 00000000 UDCS1 [R/W] B 00000000 System Reserved UDCR3 [R] B, H 00000000 UDCR2 [R] B, H 00000000 UDCS2 [R/W] B 00000000 UDCS2 [R/W] B 00000000 System Reserved AD2ERL [R/W] 00000000 00000000 AD2CR1 [R] ------XX AD2SCH [R/W] ---00000 AD2CR0 [R] XXXXXXXX AD2ECH [R/W] ---00000 (Continued) 33 A/D Converter 2 (MB91V280 only) Up Down Counter 2/3 Up Down Counter 0/1 A/D Converter
CUCR [R/W] B, H, W -------- ---00000 CUTR1 [R] B, H, W -------- 00000000 UDRC1 [W] B, H 00000000 UDCCH0 [R/W] B, H 00000000 UDCCH1 [R/W] B, H -0000000 UDRC3 [W] B, H 00000000 UDCCH2 [R/W] B, H 00000000 UDCCH3 [R/W] B, H -0000000 UDRC0 [W] B, H 00000000 UDCCL0 [R/W] B, H -0000000 UDCCL1 [R/W] B, H -0000000 UDRC2 [W] B, H 00000000 UDCCL2 [R/W] B, H -0000000 UDCCL3 [R/W] B, H -0000000 AD2ERH [R/W] 00000000 00000000 AD2CS1 [R/W] 00000000 AD2CT1 [R/W] 00010000 AD2CS0 [R, R/W] 00000000 AD2CT0 [R/W] 00101100
CUTD [R/W] B, H, W 10000000 00000000 CUTR2 [R] B, H, W 00000000 00000000
000174H
000178H 00017CH 000180H
000184H
000188H 00018CH 000190H 000194H 000198H
MB91270 Series
Address 00019CH 0001A0H 0001A4H
Register +0 +1 CMPR [R/W] B, H --000010 11111101 CMT1 [R/W] B, H, W 00000000 10000000 CANPRE [R, R/W] 00000000 PRLH0 [R/W] B, H, W XXXXXXXX PRLH2 [R/W] B, H, W XXXXXXXX PPGC0 [R/W] B, H, W 0000000X PRLH4 [R/W] B, H, W XXXXXXXX PRLH6 [R/W] B, H, W XXXXXXXX PPGC4 [R/W] B, H, W 0000000X PRLH8 [R/W] B, H, W XXXXXXXX PRLHA [R/W] B, H, W XXXXXXXX PPGC8 [R/W] B, H, W 0000000X PRLL0 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PPGC1 [R/W] B, H, W 0000000X PRLL4 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PPGC5 [R/W] B, H, W 0000000X PRLL8 [R/W] B, H, W XXXXXXXX PRLLA [R/W] B, H, W XXXXXXXX PPGC9 [R/W] B, H, W 0000000X PRLH9 [R/W] B, H, W XXXXXXXX PRLHB [R/W] B, H, W XXXXXXXX PPGCA [R/W] B, H, W 0000000X PRLL9 [R/W] B, H, W XXXXXXXX PRLLB [R/W] B, H, W XXXXXXXX PPGCB [R/W] B, H, W 0000000X PRLH5 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PPGC6 [R/W] B, H, W 0000000X PRLL5 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX PPGC7 [R/W] B, H, W 0000000X PRLH1 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PPGC2 [R/W] B, H, W 0000000X PRLL1 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX PPGC3 [R/W] B, H, W 0000000X CMCR [R/W] B, H -0010000 +2 +3
Block System Reserved
CMT2 [R/W] B, H, W 00000000 00000000 EISSR [R/W] B, H 00000000 00000000
Clock Modulator
0001A8H 0001ACH 0001B0H
CAN Clock Presc / Ext. Int. Source Sel. System Reserved
0001B4H
PPG0 to PPG3
0001B8H 0001BCH 0001C0H
System Reserved
0001C4H
PPG4 to PPG7
0001C8H 0001CCH 0001D0H
System Reserved
0001D4H
PPG8 to PPGB
0001D8H 0001DCH
System Reserved (Continued)
34
MB91270 Series
Register +0 PRLHC [R/W] B, H, W XXXXXXXX PRLHE [R/W] B, H, W XXXXXXXX PPGCC [R/W] B, H, W 0000000X +1 PRLLC [R/W] B, H, W XXXXXXXX PRLLE [R/W] B, H, W XXXXXXXX PPGCD [R/W] B, H, W 0000000X PPGTRG [R/W] B, H, W 00000000 00000000 PPGSWAP [R/W] B 00000000 CMCLKR [R/W] B ----0000 DMACA0 [R/W] 00000000 00000000 00000000 00000000 DMACB0 [R/W] 00000000 00000000 00000000 00000000 DMACA1 [R/W] 00000000 00000000 00000000 00000000 DMACB1 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 00000000 00000000 00000000 DMACB2 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 00000000 00000000 00000000 DMACB3 [R/W] 00000000 00000000 00000000 00000000 DMACA4 [R/W] 00000000 00000000 00000000 00000000 DMACB4 [R/W] 00000000 00000000 00000000 00000000 System Reserved (Continued) DMAC DMAC PPGREVC [R/W] B, H, W 00000000 00000000 +2 PRLHD [R/W] B, H, W XXXXXXXX PRLHF [R/W] B, H, W XXXXXXXX PPGCE [R/W] B, H, W 0000000X +3 PRLLD [R/W] B, H, W XXXXXXXX PRLLF [R/W] B, H, W XXXXXXXX PPGCF [R/W] B, H, W 0000000X System Reserved PPG0 to PPGF Enable / Reverse PPG0 to PPGF Output Swap Clock Monitor System Reserved PPGC to PPGF
Address
Block
0001E0H
0001E4H
0001E8H 0001ECH 0001F0H
0001F4H
0001F8H 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH
35
MB91270 Series
Address 000240H 000244H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H to 00041CH 000420H 000424H 000428H 00042CH 000430H
Register +0 +1 +2 +3 DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] B, H 00000000 DDR4 [R/W] B, H 00000000 DDR8 [R/W] B, H 00000000 DDR1 [R/W] B, H 00000000 DDR5 [R/W] B, H 00000000 DDR9 [R/W] B, H 00000000 DDR2 [R/W] B, H 00000000 DDR6 [R/W] B, H 00000000 DDR3 [R/W] B, H 00000000 DDR7 [R/W] B, H 00000000
Block DMAC
System Reserved
Bit Search
Data Direction Registers (DDRB to DDRG are only available on the MB91V280)
DDRA [R/W] B, H DDRB [R/W] B, H ------00 --000000 DDRF [R/W] B, H 00000000
DDRC [R/W] B, H DDRD [R/W] B, H DDRE [R/W] B, H 00000000 00000000 00000000 DDRG [R/W] B, H 00000000 PFR0 [R/W] B, H 00000000 PFR4 [R/W] B, H 00000000 PFR8 [R/W] B, H 00000000 PFRC [R/W] B, H 00000000 PFRG [R/W] B, H 00000000 PFR1 [R/W] B, H 00000000 PFR5 [R/W] B, H 00000000 PFR9 [R/W] B, H 00000000 PFRD [R/W] B, H 00000000 PFR2 [R/W] B, H 00000000 PFR6 [R/W] B, H 00000000 PFRA [R/W] B, H ------00 PFRE [R/W] B, H 00000000
System Reserved PFR3 [R/W] B, H 00000000 PFR7 [R/W] B, H 00000000 PFRB [R/W] B, H --000000 PFRF [R/W] B, H 00000000 Port Function Registers (PFRB to PFRG are only available on the MB91V280)
(Continued)
36
MB91270 Series
Address 000434H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H 00048CH 000490H
Register +0 +1 ICR00 [R, R/W] ---11111 ICR04 [R, R/W] ---11111 ICR08 [R, R/W] ---11111 ICR12 [R, R/W] ---11111 ICR16 [R, R/W] ---11111 ICR20 [R, R/W] ---11111 ICR24 [R, R/W] ---11111 ICR28 [R, R/W] ---11111 ICR32 [R, R/W] ---11111 ICR36 [R, R/W] ---11111 ICR40 [R, R/W] ---11111 ICR44 [R, R/W] ---11111 ICR01 [R, R/W] ---11111 ICR05 [R, R/W] ---11111 ICR09 [R, R/W] ---11111 ICR13 [R, R/W] ---11111 ICR17 [R, R/W] ---11111 ICR21 [R, R/W] ---11111 ICR25 [R, R/W] ---11111 ICR29 [R, R/W] ---11111 ICR33 [R, R/W] ---11111 ICR37 [R, R/W] ---11111 ICR41 [R, R/W] ---11111 ICR45 [R, R/W] ---11111 RSRR [R, R/W] 10000000 CLKR [R/W] 00000000 OSCR [W, R/W] 00000000 STCR [R/W] 00110011 WPR [W] XXXXXXXX TBCR [R/W] 00XXXX00 DIVR0 [R/W] 00000011 OSCCR [R/W] XXXXXXX0 CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 ICR02 [R, R/W] ---11111 ICR06 [R, R/W] ---11111 ICR10 [R, R/W] ---11111 ICR14 [R, R/W] ---11111 ICR18 [R, R/W] ---11111 ICR22 [R, R/W] ---11111 ICR26 [R, R/W] ---11111 ICR30 [R, R/W] ---11111 ICR34 [R, R/W] ---11111 ICR38 [R, R/W] ---11111 ICR42 [R, R/W] ---11111 ICR46 [R, R/W] ---11111 ICR03 [R, R/W] ---11111 ICR07 [R, R/W] ---11111 ICR11 [R, R/W] ---11111 ICR15 [R, R/W] ---11111 ICR19 [R, R/W] ---11111 ICR23 [R, R/W] ---11111 ICR27 [R, R/W] ---11111 ICR31 [R, R/W] ---11111 ICR35 [R, R/W] ---11111 ICR39 [R, R/W] ---11111 ICR43 [R, R/W] ---11111 ICR47 [R, R/W] ---11111 +2 +3
Block
System Reserved
Interrupt Control Unit
System Reserved
Clock Control Unit
System Reserved Stb. Wait Timer (Continued)
37
MB91270 Series
Register +0 +1 CSVCR [R/W] 0001XX00 PPER0 [R/W] B, H 00000000 PPER4 [R/W] B, H 00000000 PPER8 [R/W] B, H 00000000 PPERC [R/W] B, H 00000000 PPERG [R/W] B, H 00000000 PPCR0 [R/W] B, H 00000000 PPCR4 [R/W] B, H 00000000 PPCR8 [R/W] B, H 00000000 PPCRC [R/W] B, H 00000000 PPCRG [R/W] B, H 00000000 PPCR1 [R/W] B, H 00000000 PPCR5 [R/W] B, H 00000000 PPCR9 [R/W] B, H 00000000 PPCRD [R/W] B, H 00000000 PPCR2 [R/W] B, H 00000000 PPCR6 [R/W] B, H 00000000 PPCRA [R/W] B, H ------00 PPCRE [R/W] B, H 00000000 PPCR3 [R/W] B, H 00000000 PPCR7 [R/W] B, H 00000000 PPCRB [R/W] B, H --000000 PPCRF [R/W] B, H 00000000 PPER1 [R/W] B, H 00000000 PPER5 [R/W] B, H 00000000 PPER9 [R/W] B, H 00000000 PPERD [R/W] B, H 00000000 PPER2 [R/W] B, H 00000000 PPER6 [R/W] B, H 00000000 PPERA [R/W] B, H ------00 PPERE [R/W] B, H 00000000 PPER3 [R/W] B, H 00000000 PPER7 [R/W] B, H 00000000 PPERB [R/W] B, H --000000 PPERF [R/W] B, H 00000000 +2 +3
Address 000494H to 0004A8H 0004ACH 0004B0H to 0004FCH 000500H
Block
System Reserved
Clock Supervisor
System Reserved
000504H
Port Pull-up/down Enable Registers (PPERB to PPERG are only available on the MB91V280)
000508H
00050CH
000510H 000514H to 00051CH 000520H
System Reserved
000524H
Port Pull-up/down Control Registers (PPCRB to PPCRG are only available on the MB91V280)
000528H
00052CH
000530H 000534H to 00053CH
System Reserved (Continued)
38
MB91270 Series
Address 000540H 000544H 000548H 00054CH 000550H 000554H to 00055CH 000560H 000564H 000568H 00056CH 000570H 000574H 000578H 00057CH 000580H 000584H 000588H 00058CH 000590H to 0005F8H 0005FCH
Register +0 PILR0 [R/W] B, H 00000000 PILR4 [R/W] B, H 00000000 PILR8 [R/W] B, H 00000000 +1 PILR1 [R/W] B, H 00000000 PILR5 [R/W] B, H 00000000 +2 PILR2 [R/W] B, H 00000000 PILR6 [R/W] B, H 00000000 +3 PILR3 [R/W] B, H 00000000 PILR7 [R/W] B, H 00000000
Block
Port Input Level select Registers (PILRB to PILRG are only available on the MB91V280)
PILR9 [R/W] B, H PILRA [R/W] B, H PILRB [R/W] B, H 00000000 ------00 --000000
PILRC [R/W] B, H PILRD [R/W] B, H PILRE [R/W] B, H PILRF [R/W] B, H 00000000 00000000 00000000 00000000 PILRG [R/W] 00000000 IBCR0 [R/W] 00000000 ITMKH0 [R/W, R] 00----11 IBSR0 [R] 00000000 ITMKL0 [R/W] 11111111 IDAR0 [R/W] 00000000 IBCR1 [R/W] 00000000 ITMKH1 [R/W, R] 00----11 IBSR1 [R] 00000000 ITMKL1 [R/W] 11111111 IDAR1 [R/W] 00000000 IBCR2 [R/W] 00000000 ITMKH2 [R/W, R] 00----11 IBSR2 [R] 00000000 ITMKL2 [R/W] 11111111 IDAR2 [R/W] 00000000 HWDCS [R/W] B, H 00011000 ITBAH2 [R/W] ------00 ISMK2 [R/W] 01111111 ICCR2 [R/W] -0011111 ITBAL2 [R/W] 00000000 ISBA2 [R/W] -0000000 ITBAH1 [R/W] ------00 ISMK1 [R/W] 01111111 ICCR1 [R/W] -0011111 ITBAL1 [R/W] 00000000 ISBA1 [R/W] -0000000 ITBAH0 [R/W] ------00 ISMK0 [R/W] 01111111 ICCR0 [R/W] -0011111 ITBAL0 [R/W] 00000000 ISBA0 [R/W] -0000000
System Reserved
I2C 0
System Reserved
I2C 1
System Reserved
I2C 2
System Reserved System Reserved
Hardware Watchdog (Continued)
39
MB91270 Series
Address
Register +0 EPFR0 [R/W] B, H 00000000 EPFR4 [R/W] B, H 00000000 EPFR8 [R/W] B, H 00000000 EPFRC [R/W] B, H 00000000 EPFRG [R/W] B, H 00000000 PIDR0 [R] B, H XXXXXXXX PIDR4 [R] B, H XXXXXXXX PIDR8 [R] B, H XXXXXXXX PIDRC [R] B, H XXXXXXXX PIDRG [R] B, H XXXXXXXX ASR0 [R/W] 00000000 00000000 ASR1 [R/W] XXXXXXXX XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ASR3 [R/W] XXXXXXXX XXXXXXXX ACR0 [R/W] 00110*00 00000000 ACR1 [R/W] XXXX0X00 00X0XXXX ACR2 [R/W] XXXX0X00 00X0XXXX ACR3 [R/W] 01XX0X00 00X0XXXX PIDR1 [R] B, H XXXXXXXX PIDR5 [R] B, H XXXXXXXX PIDR9 [R] B, H XXXXXXXX PIDRD [R] B, H XXXXXXXX PIDR2 [R] B, H XXXXXXXX PIDR6 [R] B, H XXXXXXXX PIDRA [R] B, H ------XX PIDRE [R] B, H XXXXXXXX PIDR3 [R] B, H XXXXXXXX PIDR7 [R] B, H XXXXXXXX PIDRB [R] B, H --XXXXXX PIDRF [R] B, H XXXXXXXX +1 EPFR1 [R/W] B, H 00000000 EPFR5 [R/W] B, H 00000000 EPFR9 [R/W] B, H 00000000 EPFRD [R/W] B, H 00000000 +2 EPFR2 [R/W] B, H 00000000 EPFR6 [R/W] B, H 00000000 EPFRA [R/W] B, H ------00 EPFRE [R/W] B, H 00000000 +3 EPFR3 [R/W] B, H 00000000 EPFR7 [R/W] B, H 00000000 EPFRB [R/W] B, H --000000 EPFRF [R/W] B, H 00000000
Block
000600H
000604H
Extra Port Function Register (EPFRB to EPFRG are only available on the MB91V280)
000608H
00060CH
000610H 000614H to 00061CH 000620H 000624H 000628H 00062CH 000630H 000634H to 00063CH 000640H 000644H 000648H 00064CH
System Reserved
Input Data Direct Read Data Register (PIDRB to PDIRG are only available on the MB91V280)
System Reserved
T-Unit
(Continued)
40
MB91270 Series
Register +0 +1 AWR0 [R/W] 01110000 01011011 AWR2 [R/W] 0XXX0000 XX0X1XXX CSER [R/W] ----0001 MODR [W] XXXXXXXX DMASA0 [R/W] ----0000 00000000 00000000 DMADA0 [R/W] ----0000 00000000 00000000 DMASA1 [R/W] ----0000 00000000 00000000 DMADA1 [R/W] ----0000 00000000 00000000 DMASA2 [R/W] ----0000 00000000 00000000 DMADA2 [R/W] ----0000 00000000 00000000 DMASA3 [R/W] ----0000 00000000 00000000 DMADA30 [R/W] ----0000 00000000 00000000 DMASA4 [R/W] 00000000 00000000 00000000 DMADA4 [R/W] 00000000 00000000 00000000 System Reserved (Continued) 41 System Reserved AWR1 [R/W] XXXX0000 XX0X1XXX AWR3 [R/W] 0XXX0000 0X0X1XXX T-Unit +2 +3
Address 000650H to 00065CH 000660H 000664H 000668H to 00067CH 000680H 000684H to 0007F8H 0007FCH 000800H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 00102BH to 006FFCH
Block
Mode Register
System Reserved
DMAC
MB91270 Series
Address 007000H 007004H 007008H to 01FFFCH 020000H 020004H 020008H 02000CH 020010H 020014H 020018H 02001CH 020020H 020024H 020030H to 02003CH 020040H 020044H 020048H 02004CH 020050H 020054H
Register +0 FLCR [R/W] 0110X000 FLWC [R/W] 00000011 CTRLR0 [R, R/W] 00000000 00000001 ERRCNT0 [R] 00000000 00000000 INTR0 [R] 00000000 00000000 BRPER0 [R, R/W] 00000000 00000000 IF1CREQ0 [R, R/W] 00000000 00000001 IF1MSK20 [R, R/W] 11111111 11111111 IF1ARB20 [R/W] 00000000 00000000 IF1MCTR0 [R, R/W] 00000000 00000000 IF1DTA10 [R/W] XXXXXXXX XXXXXXXX IF1DTB10 [R/W] XXXXXXXX XXXXXXXX STATR0 [R, R/W] 00000000 00000000 BTR0 [R, R/W] 00100011 00000001 TESTR0 [R, R/W] 00000000 00000000 IF1CMSK0 [R, R/W] 00000000 00000000 IF1MSK10 [R, R/W] 11111111 11111111 IF1ARB10 [R/W] 00000000 00000000 IF1DTA20 [R/W] XXXXXXXX XXXXXXXX IF1DTB20 [R/W] XXXXXXXX XXXXXXXX +1 +2 +3
Block
Flash I/F System Reserved
CAN 0
CAN 0
System Reserved (IF1 data mirror, little endian byte ordering) IF2CREQ0 [R, R/W] 00000000 00000001 IF2MSK20 [R, R/W] 11111111 11111111 IF2ARB20 [R/W] 00000000 00000000 IF2MCTR0 [R, R/W] 00000000 00000000 IF2DTA10 [R/W] XXXXXXXX XXXXXXXX IF2DTB10 [R/W] XXXXXXXX XXXXXXXX IF2CMSK0 [R, R/W] 00000000 00000000 IF2MSK10 [R, R/W] 11111111 11111111 IF2ARB10 [R/W] 00000000 00000000 IF2DTA20 [R/W] XXXXXXXX XXXXXXXX IF2DTB20 [R/W] XXXXXXXX XXXXXXXX (Continued)
42
MB91270 Series
Address 020060H to 02007CH 020080H 020090H 0200A0H 0200B0H 0200B4H to 0200FCH 020100H 020104H 020108H 02010CH 020110H 020114H 020118H 02011CH 020120H 020124H 020130H to 02013CH 020140H 020144H 020148H
Register +0 +1 +2 +3
Block
System Reserved (IF2 data mirror, little endian byte ordering) TREQR20 [R] 00000000 00000000 NEWDT20 [R] 00000000 00000000 INTPND20 [R] 00000000 00000000 MSGVAL20 [R] 00000000 00000000 CTRLR1 [R, R/W] 00000000 00000001 ERRCNT1 [R] 00000000 00000000 INTR1 [R] 00000000 00000000 BRPER1 [R, R/W] 00000000 00000000 IF1CREQ1 [R, R/W] 00000000 00000001 IF1MSK21 [R, R/W] 11111111 11111111 IF1ARB21 [R/W] 00000000 00000000 IF1MCTR1 [R, R/W] 00000000 00000000 IF1DTA11 [R/W] XXXXXXXX XXXXXXXX IF1DTB11 [R/W] XXXXXXXX XXXXXXXX STATR1 [R, R/W] 00000000 00000000 BTR1 [R, R/W] 00100011 00000001 TESTR1 [R, R/W] 00000000 00000000 IF1CMSK1 [R, R/W] 00000000 00000000 IF1MSK11 [R, R/W] 11111111 11111111 IF1ARB11 [R/W] 00000000 00000000 IF1DTA21 [R/W] XXXXXXXX XXXXXXXX IF1DTB21 [R/W] XXXXXXXX XXXXXXXX CAN 1 (MB91V280 only) TREQR10 [R] 00000000 00000000 NEWDT10 [R] 00000000 00000000 INTPND10 [R] 00000000 00000000 MSGVAL10 [R] 00000000 00000000 System Reserved CAN 0
System Reserved (IF1 data mirror, little endian byte ordering) IF2CREQ1 [R, R/W] 00000000 00000001 IF2MSK21 [R, R/W] 11111111 11111111 IF2ARB21 [R/W] 00000000 00000000 IF2CMSK1 [R, R/W] 00000000 00000000 IF2MSK11 [R, R/W] 11111111 11111111 IF2ARB11 [R/W] 00000000 00000000 (Continued) 43
MB91270 Series
Address 02014CH 020150H 020154H 020160H to 02017CH 020180H 020190H 0201A0H 0201B0H 020200H 020204H 020208H 02020CH 020210H 020214H 020218H 02021CH 020220H 020224H 020230H to 02023CH 020240H
Register +0 +1 +2 IF2DTA21 [R/W] XXXXXXXX XXXXXXXX IF2DTB21 [R/W] XXXXXXXX XXXXXXXX +3 IF2MCTR1 [R, R/W] 00000000 00000000 IF2DTA11 [R/W] XXXXXXXX XXXXXXXX IF2DTB11 [R/W] XXXXXXXX XXXXXXXX
Block
System Reserved (IF2 data mirror, little endian byte ordering) TREQR21 [R] 00000000 00000000 NEWDT21 [R] 00000000 00000000 INTPND21 [R] 00000000 00000000 MSGVAL21 [R] 00000000 00000000 CTRLR2 [R, R/W] 00000000 00000001 ERRCNT2 [R] 00000000 00000000 INTR2 [R] 00000000 00000000 BRPER2 [R, R/W] 00000000 00000000 IF1CREQ2 [R, R/W] 00000000 00000001 IF1MSK22 [R, R/W] 11111111 11111111 IF1ARB22 [R/W] 00000000 00000000 IF1MCTR2 [R, R/W] 00000000 00000000 IF1DTA12 [R/W] XXXXXXXX XXXXXXXX IF1DTB12 [R/W] XXXXXXXX XXXXXXXX TREQR11 [R] 00000000 00000000 NEWDT11 [R] 00000000 00000000 INTPND11 [R] 00000000 00000000 MSGVAL11 [R] 00000000 00000000 STATR2 [R, R/W] 00000000 00000000 BTR2 [R, R/W] 00100011 00000001 TESTR2 [R, R/W] 00000000 00000000 IF1CMSK2 [R, R/W] 00000000 00000000 IF1MSK12 [R, R/W] 11111111 11111111 IF1ARB12 [R/W] 00000000 00000000 IF1DTA22 [R/W] XXXXXXXX XXXXXXXX IF1DTB22 [R/W] XXXXXXXX XXXXXXXX
CAN 1 (MB91V280 only)
CAN 2 (MB91V280 only)
System Reserved (IF1 data mirror, little endian byte ordering) IF2CREQ2 [R, R/W] 00000000 00000001 IF2CMSK2 [R, R/W] 00000000 00000000 (Continued)
44
MB91270 Series
(Continued) Address 020244H 020248H 02024CH 020250H 020254H 020260H to 02027CH 020280H 020290H 0202A0H 0202B0H 034000H to 03FFFCH 03A000H to 03FFFCH 080000H to 0FFFFCH Register +0 +1 +2 +3 IF2MSK22 [R, R/W] 11111111 11111111 IF2ARB22 [R/W] 00000000 00000000 IF2MCTR2 [R, R/W] 00000000 00000000 IF2DTA12 [R/W] XXXXXXXX XXXXXXXX IF2DTB12 [R/W] XXXXXXXX XXXXXXXX IF2MSK12 [R, R/W] 11111111 11111111 IF2ARB12 [R/W] 00000000 00000000 IF2DTA22 [R/W] XXXXXXXX XXXXXXXX IF2DTB22 [R/W] XXXXXXXX XXXXXXXX CAN 2 (MB91V280 only) Block
System Reserved (IF2 data mirror, little endian byte ordering) TREQR22 [R] 00000000 00000000 NEWDT22 [R] 00000000 00000000 INTPND22 [R] 00000000 00000000 MSGVAL22 [R] 00000000 00000000 TREQR12 [R] 00000000 00000000 NEWDT12 [R] 00000000 00000000 INTPND12 [R] 00000000 00000000 MSGVAL12 [R] 00000000 00000000
F-bus RAM (MB91V280) F-bus RAM (MB91F273 (S) / MB91F278 (S) ) Flash memory (MB91F273 (S) / MB91F278 (S) )
45
MB91270 Series
INTERRUPT VECTOR
Interrupt number Interrupt source Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E Interrupt level Register 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 Address 0x440 0x441 0x442 0x443 0x444 0x445 0x446 0x447 0x448 0x449 0x44A 0x44B 0x44C 0x44D 0x44E Interrupt vector Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 00FFFD4CH 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H DMA RN 6 7 8 9 10 0 3 1 4 Stop Stop Stop
Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 LIN-UART 0 reception LIN-UART 0 transmission LIN-UART 1 reception LIN-UART 1 transmission
(Continued) 46
MB91270 Series
Interrupt number Interrupt source Decimal 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Interrupt level Address 0x44F 0x450 0x451 0x452 0x453 0x454 0x455 0x456 0x457 0x458 0x459 0x45A 0x45B 0x45C 0x45D 0x45E 0x45F 0x460 0x461 0x462 0x463 0x464 0x465 0x466 0x467 0x468 0x469 0x46A 0x46B 0x46C 0x46D 0x46E 0x46F Interrupt vector Offset 380H 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H TBR default address 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H DMA RN 2 5 14 Stop Stop
HexaRegister decimal 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
LIN-UART 2 reception LIN-UART 2 transmission CAN 0 CAN 1/ICU 6/7* CAN 2* LIN-UART 3/5 reception LIN-UART 3/5 transmission LIN-UART 4/6 reception LIN-UART 4/6 transmission IC0 I C 1/UDC 2 IC2 A/D converter RTC UDC 1 Main oscillation stabilization wait timer TBT overflow PPG 0/1/4/5 PPG 2/3/6/7 PPG 8/9/C/D PPG A/B/E/F FRT 0/1 FRT 2/3 ICU 0/1/2/3 ICU 4/5 OCU 0/1/2/3 UDC 3 OCU 4/5/6/7 UDC 0 External interrupt 8/9/10/11 External interrupt 12 to 39* ROM correction interrupt DMA Delay interrupt
2 2 2
(Continued) 47
MB91270 Series
(Continued) Interrupt number Interrupt source Decimal 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Hexadecimal 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Register Address Interrupt vector Offset 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default address 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H DMA RN Stop
System reserved (REALOS) System reserved (REALOS) System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved
Used by INT instruction 80 to 255
* : CAN1, CAN2, and external interrupts 16 to 39 are only available on the MB91V280.
48
MB91270 Series
PIN STATES IN EACH CPU STATE
* Pin states in single-chip mode At initialization Port name Specified function Function name name INT8 SIN5 INT9 SOT5 INT10 SCK5 INT11 SIN6 INT12 SOT6 INT13 SCK6 INT14 INT15 TIN1 TOT1 SIN3 INT11R SOT3 SCK3 SIN4 SOT4 SCK4 PPG9 PPGB PPGD PPGF IN0 IN1 IN2 IN3 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 (Continued) Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1 Sleep Internal ROM mode vector (MD2-0 = 000) INIT RST Sub sleep In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27
49
MB91270 Series
At initialization Port name Specified function Function name name IN4 IN5 RX2 INT10R TX2 OUT4 OUT5 OUT6 OUT7 IN6 INT9R IN7 SDA0 FRCK0 SCL0 FRCK1 AIN2 SDA1 BIN2 SCL1 ZIN2 AN8 SIN2 AN9 SOT2 AN10 SCK2 AN11 BIN1 AN12 AIN1 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 Sleep Internal ROM mode vector (MD2-0 = 000) INIT RST Sub sleep
In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44
*1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1
P45
P45
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect
P46 P47 P50 P51 P52 P53 P54
P46 P47 P50 P51 P52 P53 P54 (Continued) Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled
50
MB91270 Series
At initialization Port name Specified function Function name name AN13 ZIN1 AN14 DAO0 AN15 DAO1 AN0 PPG0 AN1 PPG2 AN2 PPG4 AN3 PPG6 AN4 PPG8 AN5 PPGA AN6 PPGC AN7 PPGE AN16 INT0 AN17 INT1 AN18 INT2 AN19 INT3 AN20 INT4 AN21 INT5 AN22 INT6 SDA2 AN23 INT7 SCL2 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect Sleep Internal ROM mode vector (MD2-0 = 000) INIT RST Sub sleep In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75
P76
P76
P77
P77 (Continued) 51
MB91270 Series
At initialization Port name Specified function Function name name TIN0 ADTG INT12R TOT0 CKOT INT13R SIN0 TIN2 INT14R SOT0 TOT2 SCK0 INT15R SIN1 SOT1 SCK1 PPG1 PPG3 AIN3 PPG5 BIN3 PPG7 ZIN3 OUT0 AIN0 OUT1 BIN0 OUT2 ZIN0 OUT3 RX0 INT8R TX0 INT8-2 SIN5-2 Sleep Internal ROM mode vector (MD2-0 = 000) INIT RST Sub sleep
In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
P80
P80
P81
P81
*1
P82
P82
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect
P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0 PA1 PB0
P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0 PA1 PB0 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1
*2
(Continued)
52
MB91270 Series
At initialization Port name Specified function Function name name INT9-2 SOT5-2 INT10-2 SCK5-2 INT11-2 SIN6-2 INT12-2 SOT6-2 INT13-2 SCK6-2 OUT4-2 INT0R OUT5-2 INT1R SIN3-2 INT2R SOT3-2 INT3R SCK3-2 INT4R SIN4-2 INT5R SOT4-2 INT6R SCK4-2 INT7R PB1 PB2 PB3 PB4 PB5 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Sleep Internal ROM mode vector (MD2-0 = 000) INIT RST Sub sleep
In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
PB1 PB2 PB3 PB4 PB5 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect
*2
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled (Continued)
53
MB91270 Series
At initialization Specified Port function name Function name name PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PPG9-2 INT16 PPGB-2 INT17 PPGD-2 INT18 PPGF-2 INT19 IN0-2 INT20 IN1-2 INT21 IN2-2 INT22 IN3-2 INT23 INT24 INT25 INT26 INT27 INT28 INT29 INT30 INT31 INT32 INT33 INT34 INT35 INT36 INT37 INT38 INT39 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 Sleep Internal ROM mode vector (MD2-0 = 000) INIT RST Sub sleep
In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect
*1
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect
Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect
(Continued)
54
MB91270 Series
(Continued) At initialization Port name Specified function Function name name AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state enabled enabled disconnect *1 Sleep Internal ROM mode vector (MD2-0 = 000) INIT RST Sub sleep In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
*1 : Pins become inputs and can be used to wakeup from STOP mode when the corresponding external interrupt is enabled in ENIR and the pin is selected as an external interrupt input pin in EISSR. *2 : Pins will be available to input and can be used to restore from the STOP mode when the corresponding external interrupt is enabled in ENIR and the pin is selected as an external interrupt input pin in EPFR. : This indicates that the input function is available in this state. : Disconnects the external input at the input gate immediately adjacent to the pin . An "L" level is passed to internal circuits. Output Hi-Z : Turns the pin to high-impedance by preventing the pin drive transistor from driving. Output maintained : Indicates that pins maintain the output level they had prior to changing to this mode. In other words, the pin outputs the value in accordance with the peripheral operation if the internal peripheral that uses the output is operating, and the pin maintains its output level if the pin is set as a port. Maintain previous state : Indicates that output pins maintain the output level they had prior to this mode, or input pins continue to operate. Input enabled Input disconnect
55
MB91270 Series
* Pin states in external bus mode * The external bus interface pins will be in an output mode while the device is in the settings initialization (INIT) state. The pins is in the Hi-Z state while the INIT pin is at the "L" level. The value listed in the table is output when the INIT pin goes to the "H" level. * The external bus interface output functions for ports 2, 3, 9, E, and F can be disabled by setting EPFR. The symbols in the table indicate : B : External bus interface function mode (EPFR = 0) P : General-purpose port or peripheral function mode (EPFR = 1) At a initial/reset Port name Specified function Function name name AD00 INT8 SIN5 AD01 INT9 SOT5 AD02 INT10 SCK5 AD03 INT11 SIN6 AD04 INT12 SOT6 AD05 INT13 SCK6 AD06 INT14 AD07 INT15 Initial Value External ROM mode vector (MD2-0 = 001) Internal ROM mode vector (MD2-0 = 000) Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
P00
AD00
P01
AD01
P02
AD02 Address output (MPX) Output Hi-Z Input enabled (Data) Output Hi-Z Input disconnect
P03
AD03
Output Hi-Z Input enabled
Output Hi-Z Input enabled
*1
P04
AD04
P05
AD05
P06 P07
AD06 AD07 (Continued)
56
MB91270 Series
At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) AD08 TIN1 AD09 TOT1 AD10 SIN3 INT11R AD11 SOT3 AD12 SCK3 AD13 SIN4 AD14 SOT4 AD15 SCK4 A16 PPG9 A17 PPGB A18 PPGD A19 PPGF A20 IN0 A21 IN1 A22 IN2 A23 IN3 AD08 AD09 Address output (MPX) Output Hi-Z Output Hi-Z Input Input enabled (Data) disconnect Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
P10 P11
P12
AD10
Output Hi-Z Input enabled
Output Hi-Z Input enabled
*1
P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27
AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 Output 0xFF A20 A21 A22 A23
Output Hi-Z Input enabled
Output Hi-Z Input enabled
Address output (MPX) Output Hi-Z Output Hi-Z Input Input enabled (Data) disconnect
B : Address output Output Hi-Z Input enabled P : Maintain previous state
Output Hi-Z Input disconnect
*2
(Continued)
57
MB91270 Series
At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) AS IN4 RD IN5 WR0 RX2 INT10R WR1 TX2 OUT4 OUT5 RDY OUT6 AS *2 RD "H" level output WR0 B : "H" level output P : Maintain previous state *1 *2 *2 Output Maintain previous state Hi-Z Output Hi-Z Input enabled Input B : Output Hi-Z disconnect P : Maintain previous state B: B: "H" level Clock output output P37 SYSCLK OUT7 P37 Clock output P: Maintain previous state P: Maintain previous state *2 Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
P30 P31
P32
P33 P34 P35 P36
WR1 P34 P35 RDY Output Hi-Z Input enabled
P40 P41 P42 P43 P44
IN6 INT9R IN7 SDA0 FRCK0
P40 P41 P42 P43 P44 (Continued) Same as single-chip mode
58
MB91270 Series
At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) SCL0 AIN2 FRCK1 SDA1 BIN2 SCL1 ZIN2 AN8 SIN2 AN9 SOT2 AN10 SCK2 AN11 BIN1 AN12 AIN1 AN13 ZIN1 AN14 DAO0 AN15 DAO1 AN0 PPG0 AN1 PPG2 AN2 PPG4 AN3 PPG6 AN4 PPG8 AN5 PPGA AN6 PPGC AN7 PPGE P45 Same as single-chip mode Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
P45
P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67
P46 P47 P50 P51 P52 P53
Same as single-chip mode P54 P55 P56 P57 P60 P61 P62 P63 Same as single-chip mode P64 P65 P66 P67 (Continued) 59
MB91270 Series
At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) AN16 INT0 AN17 INT1 AN18 INT2 AN19 INT3 AN20 INT4 AN21 INT5 AN22 INT6 SDA2 AN23 INT7 SCL2 TIN0 ADTG INT12R TOT0 CKOT INT13R SIN0 TIN2 INT14R SOT0 TOT2 SCK0 INT15R SIN1 SOT1 SCK1 P70 P71 P72 P73 P74 P75 Same as single-chip mode In stop mode In RTC mode Remarks HIZ = 0 HIZ = 1
Sleep Sub sleep
P70 P71 P72 P73 P74 P75
P76
P76
P77
P77
P80
P80
P81
P81
P82
P82 Same as single-chip mode P83 P84 P85 P86 P87 (Continued)
P83 P84 P85 P86 P87
60
MB91270 Series
At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) CS0 PPG1 CS1 PPG3 AIN3 CS2 PPG5 BIN3 CS3 PPG7 ZIN3 OUT0 AIN0 OUT1 BIN0 OUT2 ZIN0 OUT3 RX0 INT8R TX0 INT8-2 SIN5-2 INT9-2 SOT5-2 INT10-2 SCK5-2 INT11-2 SIN6-2 INT12-2 SOT6-2 INT13-2 SCK6-2 CS0 Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
P90
P91
CS1 Output Hi-Z "H" level output Input enabled
B : "H" level output P : Maintain previous state
P92
CS2
Output Hi-Z Input disconnect
*2
P93
CS3
P94 P95 P96 P97 PA0 PA1 PB0 PB1 PB2 PB3 PB4 PB5
P94 P95 P96 P97 PA0 PA1 PB0 PB1 PB2 Same as single-chip mode PB3 PB4 PB5 (Continued) Same as single-chip mode
Same as single-chip mode
61
MB91270 Series
At a initial/reset Port name Specified function Function name name OUT4-2 INT0R OUT5-2 INT1R SIN3-2 INT2R SOT3-2 INT3R SCK3-2 INT4R SIN4-2 INT5R SOT4-2 INT6R SCK4-2 INT7R PPG9-2 INT16 PPGB-2 INT17 PPGD-2 INT18 PPGF-2 INT19 IN0-2 INT20 IN1-2 INT21 IN2-2 INT22 IN3-2 INT23 Initial Value External ROM mode vector (MD2-0 = 001) Internal ROM mode vector (MD2-0 = 000) Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
PC0 PC1 PC2 PC3 Same as single-chip mode PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 (Continued) Same as single-chip mode Same as single-chip mode
62
MB91270 Series
At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) A00 INT24 A01 INT25 A02 INT26 A03 INT27 A04 INT28 A05 INT29 A06 INT30 A07 INT31 A08 INT32 A09 INT33 A10 INT34 A11 INT35 A12 INT36 A13 INT37 A14 INT38 A15 INT39 AN24 AN25 AN26 AN27 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 PG0 PG1 PG2 PG3 (Continued) Same as single-chip mode B : Address output "H" level output Output Hi-Z Input enabled P : Maintain previous state Output Hi-Z Input disconnect B : Address output "H" level output Output Hi-Z Input enabled P : Maintain previous state Output Hi-Z Input disconnect Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3
*1 *2
*1 *2
63
MB91270 Series
(Continued) At a initial/reset Port name Specified function Function name name AN28 AN29 AN30 AN31 PG4 PG5 PG6 PG7 Same as single-chip mode Initial Value External ROM mode vector (MD2-0 = 001) Internal ROM mode vector (MD2-0 = 000) Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 In stop mode In RTC mode
PG4 PG5 PG6 PG7
*1 : Pins become inputs and can be used to wakeup from STOP mode when the corresponding external interrupt is enabled in ENIR and the pin is selected as an external interrupt input pin in EISSR. *2 : Outputs go to Hi-Z at power on or while the INIT pin is at the "L" level starting from the falling edge on the INIT pin. Input enabled Input disconnect : This indicates that the input function is available in this state. : Disconnects the external input at the input gate immediately adjacent to the pin . An "L" level is passed to internal circuits. Output Hi-Z : Turns the pin to high-impedance by preventing the pin drive transistor from driving. Output maintained : Indicates that pins maintain the output level they had prior to changing to this mode. In other words, the pin outputs the value in accordance with the peripheral operation if the internal peripheral that uses the output is operating, and the pin maintains its output level if the pin is set as a port. Maintain previous state : Indicates that output pins maintain the output level they had prior to this mode, or input pins continue to operate.
64
MB91270 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage Input voltage Output voltage "L" level maximum output current* "L" level average output current*3 "L" level total maximum output current "L" level total average output current*4 "H" level maximum output current* "H" level average output current*
3 2 2
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 40 - 40 - 55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 VCC + 0.3 15 4 120 50 - 15 -4 - 120 - 50 500 + 105 + 85 + 150 2
Unit V V V V V mA mA mA mA mA mA mA mA mW C C C mA *5
Remarks
AVCC AVRH VI VO IOL1 IOLAV1 IOL1 IOLAV1 IOH1 IOHAV1 IOH1 IOHAV1 PD TA Tstg IIHH
4
AVCC = VCC*1 AVCC AVRH
"H" level total maximum output current "H" level total average output current* Power consumption Operating temperature Storage temperature +B Input rating (Maximum clamp current)
Single-chip mode External bus mode
*1 : Ensure that AVCC does not exceed VCC when the power is turned on. *2 : The maximum output current specifies the peak current for an individual pin. *3 : The average output current specifies the average current that flows through an individual pin over a period of 100 ms. The average value is the operating current x operation ratio. *4 : The total average output current specifies the average current that flows through all of the pins over a period of 100 ms. The average value is the operating current x operation ratio. *5 : The +B input rating specifies the current for an individual pin. [Pins applicable] P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0, PA1, PB0 to PB5, PC0 to PC7, PD0 to PD7, PE0 to PE7, PF0 to PF7, PG0 to PG7 (+B input to P56 and P57 not allowed on the MB91V280.)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
65
MB91270 Series
[ For +B input (12V to 16V) ] 1. Do not connect the +B potential directly to a microcontroller pin. 2. Always place a current-limiting resistor between the +B signal and microcontroller pins. IIHH = 2mA per pin (Max) [during normal operation and during transients such as when turning the power on or off] 3. Although the internal protection diode in the microcontroller causes the potential between the +B input-limiting resistor and microcontroller pin to be equal to the VCC + on voltage of the protection diode, do not use a circuit structure that obstructs this operation or that causes this potential to be exceeded.
Sample recommended circuits:
Protection diode
IIHH
Current-limiting resistor + B input (0 V to 16 V)
66
MB91270 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol VCC AVCC Power supply voltage VCC AVCC VCC Value Min 4.5 3.5 3.0 Max 5.5 5.5 5.5 Unit V V V Remarks Normal operation Excluding A/D converter operation Maintain RAM data during STOP mode Use a ceramic capacitor or a capacitor of similar frequency characteristics. On the Vcc pin, use a bypass capacitor with a larger capacity than that of Cs. Single-chip mode External bus mode
Smoothing capacitor*
CS
1 ( 50 % tolerance)
F
Operating temperature
TA
- 40 - 40
+ 105 + 85
C C
* : Refer to the following figure for connection of smoothing capacitor Cs. * C Pin Connection Diagram
C
CS
VSS
AVSS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
67
MB91270 Series
3. DC Characteristics
(TA : Recommended Operating Conditions, VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V) Parameter SymCondiPin name bol tions VIHS VIHC "H" level input voltage VIHT VIHM VIHI VILS VILC "L" level input voltage VILT VILM VILI ICC ICCS Power supply current ICCL ICCSL ICCR32 ICCR4 ICCH Input leak current Input capacitance Pull-up resistor Pull-down resistor IIL CIN MD0 MD1 MD2 INIT MD0 MD1 MD2 INIT VCC VCC VCC VCC VCC VCC VCC *2 *3 *4 *5 *6 *7 *8 *9 *10 Value Min 0.8 x VCC 0.7 x VCC 2.1 VCC - 0.3 0.8 x VCC VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -5 25 Typ 100 70 40 20 400 300 200 700 20 5 Max VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.5 x VCC 0.3 x VCC 0.8 VSS + 0.3 0.2 x VCC 120 90 55 30 700 600 300 1000 100 5 15 Unit V V V V V V V V V V mA Normal operation*11 mA Normal operation*11 mA SLEEP operation*11 mA SLEEP operation*11 A A A A A A pF Selectable except for P44 to P47, P56, P57, P76, and P77 Selectable except for P44 to P47, P56, P57, P76, and P77 (Continued) Sub operation Sub-SLEEP operation 32 kHz clock operation *12 4 MHz clock operation*12 STOP All input pins CMOS automotive input CMOS Schmitt input TTL input*1 Remarks CMOS automotive input CMOS Schmitt input TTL input*1
RUP
50
100
k
RDOWN
25
50
100
k
68
MB91270 Series
(Continued) Parameter Symbol Pin name Conditions Value Min Typ Max 0.4 Unit Remarks Other than P44 to P47, P76 and P77 Pins also used for I2C Other than P44 to P47, P76 and P77 Pins also used for I2C
"H" level Output voltage
VOH
IOH = - 4 mA VCC - 0.5
V
VOHI
P44 to P47 IOH = - 3 mA VCC - 0.5 P76, P77 IOL = 4 mA
V
"L" level Output voltage
VOL
V
VOLI
P44 to P47 IOL = 3 mA P76, P77
0.4
V
*1 : In external bus mode, only P00 to P07, P10 to P17, and P36 can be selected. *2 : CLKB = 32 MHz, CLKP = 32 MHz, CLKT = 16 MHz, CANCLK = 16 MHz *3 : CLKB = 32 MHz, CLKP = 8 MHz, CLKT = 4 MHz, CANCLK = 8 MHz *4 : CPU halted for case *2. *5 : CPU halted for case *3. *6 : CLKB = CLKP = CLKT = CANCLK = 32 kHz, TA = + 25 C *7 : CPU halted for case *6 *8 : CPU and peripheral circuits halted, main oscillation halted, 32 kHz clock operation, TA= + 25 C *9 : CPU and peripheral circuits halted, sub-oscillation halted, 4 MHz clock operation, TA= + 25 C *10 : CPU and peripheral circuits halted, all oscillation circuits halted, TA = + 25 C *11 : The current consumption values for normal operation mode and SLEEP mode assume that the peripheral circuits are operating at maximum capacity. *12 : The current consumption value for clock mode operation does not include the consumption of the external oscillator.
69
MB91270 Series
4. Flash Memory Program and Erase Characteristics
Parameter Sector erase time Chip erase time Half-word write time Chip write time Erase/Write cycle Data retention time Conditions TA = + 25 C VCC = 5.0 V TA = + 25 C VCC = 5.0 V TA = + 25 C VCC = 5.0 V TA = + 25 C VCC = 5.0 V Average TA = + 85 C Value Min 10000 20* Typ 1 14 16 2.1 Max 5 3600 Unit s s s s cycle year Remarks Excludes time for internal write prior to erase. Excludes time for internal write prior to erase. Excludes system-level overhead time. Excludes system-level overhead time.
* : Calculated value based on technology reliability test data. (Value calculated using the Arrhenius equation for the burn-in test results with an average temperature of + 85 C.)
70
MB91270 Series
5. AC Characteristics
(TA : Recommended Operating Conditions, VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V) Parameter Source oscillation clock frequency Source oscillation clock cycle time Input clock pulse width Input clock rise time and fall time Internal operation clock frequency Internal operation clock cycle time Symbol FC FCA tCYL tCYLL PWH PWL tcr, tcf FCP tCP Pin name X0, X1 X0A, X1A X0, X1 X0A, X1A X0 Conditions Value Min 83.3 10 30 31.25 Typ 4 32.768 250 30.5 Max 12 100 5 32 Unit MHz kHz ns s ns Use a duty ratio in the range 40 % to 60 %. When external clock is used When main clock, PLL clock are used. When main clock, PLL clock are used. Remarks
X0
ns MHz ns
X0, X1 Clock Timing
tCYL
X0
0.8 VCC 0.2 VCC PWH tcf PWL tcr
71
MB91270 Series
* Operation Assurance Range
Relation between internal operation clock frequency and power supply voltage Recommended operation range (A/D converter accuracy guarantee range) Operation Assurance Range
5.5
Power supply voltage VCC (V)
4.5 3.5
PLL operation guarantee range
2
8
32
Internal operation clock frequency FCP (MHz) Note : Use a PLL operation stabilization wait time of 500 s or more.
Relation between oscillation clock frequency and internal operation clock Internal operation clock frequency PLL clock Main clock PLL multi- PLL multi- PLL multi- PLL multi- PLL multiplication plication plication plication plication rate = 2 rate = 3 rate = 4 rate = 6 rate = 8 4 MHz Oscillation clock frequency 8 MHz 12 MHz 2 MHz 4 MHz 6 MHz 8 MHz 16 MHz 24 MHz 12 MHz 24 MHz 16 MHz 32 MHz 24 MHz 32 MHz
Sample oscillation circuit
X0
X1 R
C1
C2
72
MB91270 Series
The AC standards assume the following measurement reference voltages. Input signal waveform Output signal waveform Hysteresis input pin
0.7 VCC 0.3 VCC
Output pin
4.6 V 0.4 V
Hysteresis input pin (Automotive)
0.8 VCC 0.5 VCC
TTL input pin
2.1 V 0.8 V
73
MB91270 Series
* Reset input (TA : Recommended Operating Conditions, VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin name Conditions Value Min 10 INIT input time tINTL INIT 300 8 Max Unit s s ms At STOP At power-on Remarks
tINTL
INIT
0.2 VCC 0.2 VCC
The following reset input standard should be satisfied as RAM data protection standard.
VCC (V) At drop of 4.0 3.5 V * : tCP : Period of the internal base clock.
Voltage drop time Min 256 tCP* Max
Extarnal reset input standard (INIT) Min 300 s Max
VCC
4V 3.5 V 3.5 V
INIT
300 s or more
256 tCP
To protect RAM data, input INIT of 256 tCP or more before voltage drop at VCC = 3.5 V or less.
74
MB91270 Series
* UART Timing (TA : Recommended Operating Conditions, VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL SCKx tSLSH tSLOV tIVSH tSHIX SCKx SOTx SCKx SINx 4 tCP 60 60 150 ns ns ns ns External shift clock mode Output pin capacitance is CL = 80 pF + 1 x TTL Pin name Conditions SCKx SCKx SOTx SCKx SINx Value Min 8 tCP - 80 100 60 4 tCP Max + 80 Unit ns ns ns ns ns Internal shift clock mode Output pin capacitance is CL = 80 pF + 1 x TTL Remarks
Parameter Serial clock cycle time SCKSOT delay time Valid SINSCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCKSOT delay time Valid SINSCK SCK valid SIN hold time
Note : These are AC Characteristics in the clock synchronous mode. CL is the load capacitance connected to the pin for testing.
75
MB91270 Series
* Internal shift clock mode
tSCYC
SCKx
0.8 V tSLOV
2.4 V 0.8 V
SOTx
2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.5 VCC
SINx
0.5 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.6 VCC tSLOV 2.4 V 0.6 VCC 0.8 VCC
SCKx
SOTx
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.5 VCC
SINx
0.5 VCC
76
MB91270 Series
* Timer input timing (TA : Recommended Operating Conditions, VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V) Symbol tTIWH tTIWL Pin name TINx INx Conditions Value Min 4 tCP Max Unit ns Remarks
Parameter Input pulse width
tTIWH
tTIWL
TINx INx
0.8 VCC
0.8 VCC 0.5 VCC 0.5 VCC
77
MB91270 Series
6. Electrical Characteristics for the A/D Converter
* Electrical characteristics Symbol VOT VFST tSMP tCMP tCNV IAIN VAIN AVRH IA IAH IR IRH (TA : Recommended Operating Conditions, VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V) Pin name AN0 to AN23 AN0 to AN23 AN0 to AN23 AN0 to AN23 AVRH AVCC AVRH AN0 to AN31 Value Min Typ Max 10 3.0 2.5 1.9 Unit bit LSB LSB LSB V V s s s A V V mA A A A LSB *4 VAVRH = 5.0 V *4 1 LSB = (AVRH - AVSS) / 1024 *1 *2 *3 VAVSS VAIN VAVCC Remarks
Parameter Resolution Total error Nonlinear error Differential linear error Zero transition voltage Full-scale transition voltage Sampling time Compare time A/D conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supplying current Interchannel disparity
AVSS AVSS AVSS - 1.5 LSB + 0.5 LSB + 2.5 LSB AVRH AVRH AVRH - 3.5 LSB - 1.5 LSB + 0.5 LSB 1.375 1.375 2.750 0 4.0 2.4 600 10 AVRH AVCC 4.7 5 900 5 4
*1 : For FCP = 32 MHz, tSMP = (Rext + Rin) x Cin x 7 = ST x CLKP period = 2 ch x 31.25 ns = 1.375 s *2 : For FCP = 32 MHz, tCMP = CKIN x 11 = CT x CLKP period x 11 = 4 h x 31.25 ns x 11 = 1.375 s *3 : For FCP = 32 MHz, this is equivalent to the conversion time per channel when tSMP and tCMP are selected. *4 : Specifies the power supply current when the A/D converter is not operating and the CPU is in stop mode (Vcc = AVcc = AVRH = 5.0 V) Notes : * The error becomes proportionately larger as the AVRH voltages go lower. * Use the device with external circuits of the following output impedance rS for analog inputs : External circuit output impedance rS = 5 k (Max) * If the output impedance of the external circuit is too high, the analog voltage sampling time may be insufficient. * If inserting a capacitor between the external circuit and an input pin to prevent direct current flow, select a capacitance several thousand times larger than CSH to minimize the capacitive voltage divider effect due to the CSH sampling capacitor in the chip.
78
MB91270 Series
* Analog input equivalent circuit Microcontroller internal circuit External circuit Input pin AN0
rS RSH CSH
Comparator Input pin AN7
VS
S/H circuit Analog channel selector
< Recommended parameter values for each component > rS : under 5 k RSH = Approx. 2.5 k CSH = Approx. 10 pF Note : Parameter values for each component are indicative design values.
79
MB91270 Series
* Definition of terminology Resolution Represents the change in analog signal enabled to be detected by the A/D converter. For 10-bit conversion, the analog voltage can be resolved into 210 = 1024 increments. Total error This error indicates the difference between actual and theoretical values, and is the total value of errors that results from offset error, gain error, nonlinear error, and noise. Linearity error Represents the difference between the actual conversion characteristic and the line between the zero transition point ("00 0000 0000" "00 0000 0001") and full scale transition point ("11 1111 1110" "11 1111 1111"). Differential linear error Deviation of input voltage, which is required for changing output code by 1 LSB, from a desired value.
80
MB91270 Series
* Conversion characteristics for 10-bit A/D converter
11 1111 1111 11 1111 1110 11 1111 1101 11 1111 1100
1 LSB x N + VOT
Digital output
Linearity error
00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N+1)T VFST
Analog input VOT = AVSS + 0.5 LSB [V] (theoretical value) VFST = AVRH - 1.5 LSB [V] (theoretical value) VFST = Digital output voltage at which transition from (N - 1) to N occurs. 1 LSB = Linearity error = Differential linear error = VFST - VOT 1022 VNT - (1 LSB x N + VOT) 1 LSB V (N + 1) T - VNT 1 LSB -1 [LSB] [LSB]
81
MB91270 Series
ORDERING INFORMATION
Part number MB91V280CR MB91F273SPMC MB91F273PMC MB91F278SPMC MB91F278PMC Package 401-pin ceramic PGA (PGA-401C-A02) 100-pin plastic LQFP (FPT-100P-M05) 100-pin plastic LQFP (FPT-100P-M05) 100-pin plastic LQFP (FPT-100P-M05) 100-pin plastic LQFP (FPT-100P-M05) Remarks Evaluation model Single clock model Dual clock model Single clock model Dual clock model
82
MB91270 Series
PACKAGE DIMENSIONS
401-pin ceramic PGA Lead pitch Pin matrix Sealing method 2.54 interstitial 37 Metal seal
(PGA-401C-A02)
401-pin ceramic PGA (PGA-401C-A02)
48.26 0.55 SQ (1.900 .022)
2.54 (.100) TYP
0.40 0.10 DIA (.016 .004)
1.00 (.039) DIA TYP (4 PLCS)
45.72 (1.800) REF
INDEX AREA
1.20 0.25 (.047 .010) 3.40 0.40 (.134 .016) 5.27 (.207) MAX
1.02 (.040) C TYP (4 PLCS)
EXTRA INDEX PIN
C
1994 FUJITSU LIMITED R401002SC-2-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued)
83
MB91270 Series
(Continued)
100-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 x 14.0 mm Gullwing Plastic mold 1.70 mm MAX 0.65g P-LFQFP100-14x14-0.50
(FPT-100P-M05)
Code (Reference)
100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
* 14.000.10(.551.004)SQ
75 51
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
76
50
0.08(.003) Details of "A" part
INDEX
1.50 -0.10 .059 -.004 (Mounting height)
26
+0.20
+.008
100
0.100.10 (.004.004) (Stand off) 0.25(.010)
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
1
25
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
0.1450.055 (.0057.0022)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
84
MB91270 Series
MAIN CHANGES IN THIS EDITION
Page Section
Change Results Changed the name of the series as follows: MB91270/280 series MB91270 series Changed the following part numbers: MB91F272/F272S/V280 MB91F273 (S) /F278(S) / MB91V280 Changed the table due to the change of part numbers Changed "* Max 120 ports" to "* Max 82 ports" Changed the table of the product lineup due to the change of part numbers. Changed the pin names Changed the pin names Changed the memory map due to the change of part numbers Changed the block name for the 00015CH, 000160H Changed the block names for 03A000H to 03FFFCH, 080000H to 0FFFFCH
2 3 5 6 28 33 45 46
FEATURES * Built-in memory FEATURES * I/O port PRODUCT LINEUP PIN ASSIGNMENT MEMORY MAP I/O MAP
7, 10, 11, 14 PIN FUNCTION
INTERRUPT VECTOR
Changed the interrupt source Instruction break exception System reserved, Operand break trap System reserved Changed the description in *2 Changed the pin names Changed the table due to the change of part numbers
55 56, 58, 61, 64 82
PIN STATES IN EACH CPU STATE * Pin states in single-chip mode PIN STATES IN EACH CPU STATE * Pin states in external bus mode ORDERING INFORMATION
The vertical lines marked in the left side of the page show the changes.
85
MB91270 Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
F0703

▲Up To Search▲

Price & Availability of MB91F278SPMC

	To Download MB91F278SPMC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .